On Fri, Mar 9, 2018 at 8:02 PM, Guenter Roeck <linux@xxxxxxxxxxxx> wrote: > On 03/09/2018 07:28 PM, Brian Norris wrote: >> I guess I could mention it. I was assuming that was an intended behavior >> of the existing driver: that we set resp_mode=0 (via clobber), so we >> always get a system reset (we don't try to handle any interrupt in this >> driver). >> > I don't think it was intended behavior. We don't even know for sure (or at > least > I don't know) if all implementations of this IP have the same configuration > bit > layout. All we can do is hope for the best. Huh, OK. I did try to look for any sort of generic DesignWare register documentation, and I couldn't find one easily (even with a proper Synopsys account -- maybe I wasn't looking in the right place). But besides the Rockchip TRMs, I did find some openly accessible Altera SoCFPGA docs [1] which also use this, and they have a few things to add: (1) they have the same 'reset pulse length' field, except it's labeled RO (2) they have the same 'response mode' field (3) the docs for the entire register say: "The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior." So, that pretty well corroborates my patch. Nice. > Still, clobbering just 1 bit is better than clobbering 30 bit. Yeah, that's the idea. Well, as long as it's only the 1 bit I want to clobber ;) I guess if we really find that any of this becomes more problematic (and varies enough from IP to IP), then we'll need chip-specific compatible properties. Brian [1] e.g. https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_5v4.pdf -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
