Jisheng,
On Wed, Jan 21, 2015 at 9:22 PM, Jisheng Zhang <jszhang@xxxxxxxxxxx> wrote:
> Dear Doug,
>
> On Wed, 21 Jan 2015 15:17:22 -0800
> Doug Anderson <dianders@xxxxxxxxxxxx> wrote:
>
>> On some dw_wdt implementations the "top" register may be initted to 0
>> at bootup. In such a case, each "pat" of the watchdog will reset the
>> timer to 0xffff. That's pretty short.
>
> + Guenter Roeck
>
> This should have been fixed by dfa07141e7a792("watchdog: dw_wdt: initialise
> TOP_INIT in dw_wdt_set_top()")
I will admit that I'm testing on a tree that doesn't have your patch
(I'm on a 3.14 kernel with lots of backports). ...but I did try
cherry-picking your patch before I wrote up mine and it didn't fix my
problem. I believe that the watchdog that's in Rockchip rk3288 must
be a slightly different version of the IP block than you're working
with.
Specifically I see the register WDT_TORR that has an offset of 0x4.
That's the RANGE_REG in your code. It shows bits 3:0 set the timeout
period (0 = 0xffff and 15 = 0x7fffffff). It shows bits 31:4 as
"reserved".
> In fact, my original fix is as similar as your patch
>
> http://www.spinics.net/lists/arm-kernel/msg363658.html
Yup, except that I pat the watchdog before enabling it and you pat it
after... It probably doesn't matter as long as the two instructions
are within 2.5ms of each other, but it seems nice to be safer.
-Doug
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