On Fri, Nov 25, 2016 at 05:28:01PM +0000, Mark Rutland wrote: > On Fri, Nov 25, 2016 at 05:49:45PM +0100, Christian Borntraeger wrote: > > On 11/25/2016 05:17 PM, Peter Zijlstra wrote: > > There were several cases that I found during writing the *ONCE stuff. > > For example there are some 32bit ppc variants with 64bit PTEs. Some for > > others (I think sparc). > > We have similar on 32-bit ARM w/ LPAE. LPAE implies that a naturally > aligned 64-bit access is single-copy atomic, which is what makes that > ok. > > > And the mm/ code is perfectly fine with these PTE accesses being done > > NOT atomic. > > That strikes me as surprising. Is there some mutual exclusion that > prevents writes from occuring wherever a READ_ONCE() happens to a PTE? > > Otherwise, how is tearing not a problem? Does it have some pattern like > the lockref cmpxchg? On x86 PAE we play silly games, see arch/x86/mm/gup.c:gup_get_ptr(). Those two loads really should be READ_ONCE()/LOAD_SINGLE(). _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linuxfoundation.org/mailman/listinfo/virtualization
