On Thu, Mar 21, 2013 at 09:04:48AM -0700, H. Peter Anvin wrote: > On 03/21/2013 08:58 AM, Michael S. Tsirkin wrote: > >> > >> Most of them do really ugly hacks in hardware (like putting in a "back > >> door" in config space) to make that possible. > > > > config space register that let us access > > registers within BAR actually sounds pretty reasonable. > > Way better than an I/O BAR. > > > > It is really, really, nasty, not to mention slow. Almost everything we do is through DMA, except a single write to start transmit and a single read to clear interrupts. So all it means is we do 2 io writes or reads per packet instead of 1. Seems harmless enough. A bit slower than native but should be good enough for BIOS. Needs no resources at all. Why nasty? What's not to like? > >>> Problem is, BIOS and OS normally assume failure to allocate > >>> any resources means card won't function and disable it. > >>> So it does not seem to be worth it to have such a > >>> device specific failover ability. > >>> > >> > >> That is a violation of the PCIe spec; the PCIe spec specifically states > >> that failure to allocate an I/O BAR should still allow the device to > >> function. > > > > Where does it say this? > > In PCI Express 1.1 base, it is section 1.3.2.2, third bullet. > > -hpa Thanks. Same place in latest 3.0: A PCI Express Endpoint must not depend on operating system allocation of I/O resources claimed through BAR(s). A PCI Express Endpoint must not generate I/O Requests. of course this only applies to express :) -- MST _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linuxfoundation.org/mailman/listinfo/virtualization
