On Mon, 12 Dec 2011 13:10:08 -0500, Don Dutile <ddutile@xxxxxxxxxx> wrote:
> On 12/12/2011 06:49 AM, Michael S. Tsirkin wrote:
> > On Mon, Dec 12, 2011 at 09:15:03AM +1030, Rusty Russell wrote:
> >> On Sun, 11 Dec 2011 11:42:56 +0200, "Michael S. Tsirkin"<mst@xxxxxxxxxx> wrote:
> >>> On Thu, Dec 08, 2011 at 09:09:33PM +1030, Rusty Russell wrote:
> >>>> +/* There is no iowrite64. We use two 32-bit ops. */
> >>>> +static void iowrite64(u64 val, const __le64 *addr)
> >>>> +{
> >>>> + iowrite32((u32)val, (__le32 *)addr);
> >>>> + iowrite32(val>> 32, (__le32 *)addr + 1);
> >>>> +}
> >>>> +
> >>>
> >>> Let's put addr_lo/addr_hi in the structure then,
> >>> to make the fact this field is not atomic explicit?
> >>
> >> Good point, assuming I haven't missed something.
> >>
> >> Are 64-bit accesses actually unknown in PCI-land? Or is this a limited
> >> availability thing?
> >>
> >> Thanks,
> >> Rusty.
> >
> > I think PCI can optionally support atomic 64 bit accesses, but not all
> > architectures can generate them.
> >
> yes. PCI(e) support atomic 64-bit ops; it's dependent on CPU & chipset interface
> to PCI that determines ability to generate a 64-bit length xaction.
Does this mean it's possible to detect inside Linux? I'd like to use it
if we can, but if everyone is really going to do two 32 bit writes, then
we should just define it that way.
Thanks,
Rusty.
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