On Thu, May 21, 2009 at 03:50:18PM +0100, Paul Brook wrote: > > >>> kvm has no business messing with the PCI device code. > > >> > > >> kvm has a fast path for irq injection. If qemu wants to support it we > > >> need some abstraction here. > > > > > > Fast path from where to where? Having the PCI layer bypass/re-implement > > > the APIC and inject the interrupt directly into the cpu core sounds a > > > particularly bad idea. > > > > kvm implements the APIC in the host kernel (qemu upstream doesn't > > support this yet). The fast path is wired to the in-kernel APIC, not > > the cpu core directly. > > > > The idea is to wire it to UIO for device assignment, to a virtio-device > > implemented in the kernel, and to qemu. > > I still don't see why you're trying to bypass straight from the pci layer to > the apic. Why can't you just pass the apic MMIO writes to the kernel? You've > presumably got to update the apic state anyway. > > Paul As far as I can tell, at least on Intel, MSI interrupts are not MMIO writes. They are PCI memory writes to a hard-coded address range that are passed to APIC. I don't think MMIO writes can triger MSI, or at least this does not seem to be documented. -- MST _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linux-foundation.org/mailman/listinfo/virtualization
