On Thu, May 21, 2009 at 02:09:32PM +0100, Paul Brook wrote: > > > A tight coupling between PCI devices and the APIC is just going to cause > > > us problems later one. I'm going to come back to the fact that these are > > > memory writes so once we get IOMMU support they will presumably be > > > subject to remapping by that, just like any other memory access. > > > > I'm not suggesting the qemu_irq will extend all the way to the apic. > > Think of it as connecting the device core with its interrupt unit. > > > > > Even ignoring that, qemu_irq isn't really the right interface. A MSI is a > > > one- off event, not a level state. OTOH stl_phys is exactly the right > > > interface. > > > > The qemu_irq callback should do an stl_phys(). The device is happy > > since it's using the same API it uses for non-MSI. > > MSI provides multiple edge triggered interrupts, whereas traditional mode > provides a single level triggered interrupt. My guess is most devices will > want to treat these differently anyway. So, is qemu_send_msi better than qemu_set_irq. > Either way, this is an implementation detail between pci.c and individual > devices. It has nothing to do with the APIC. > > Paul -- MST _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linux-foundation.org/mailman/listinfo/virtualization
