Although segment handling in i386 and x86_64 are very different, there's a common part. Put them in segment.h instead of arch specific headers Signed-off-by: Glauber de Oliveira Costa <gcosta@xxxxxxxxxx> --- include/asm-x86/segment.h | 16 ++++++++++++++++ include/asm-x86/segment_32.h | 22 ---------------------- include/asm-x86/segment_64.h | 17 ----------------- 3 files changed, 16 insertions(+), 39 deletions(-) diff --git a/include/asm-x86/segment.h b/include/asm-x86/segment.h index b3a7a3e..3c9b306 100644 --- a/include/asm-x86/segment.h +++ b/include/asm-x86/segment.h @@ -11,4 +11,20 @@ #define get_kernel_rpl() 0 #endif +/* User mode is privilege level 3 */ +#define USER_RPL 0x3 +/* LDT segment has TI set, GDT has it cleared */ +#define SEGMENT_LDT 0x4 +#define SEGMENT_GDT 0x0 + +/* Bottom two bits of selector give the ring privilege level */ +#define SEGMENT_RPL_MASK 0x3 +/* Bit 2 is table indicator (LDT/GDT) */ +#define SEGMENT_TI_MASK 0x4 + +#define IDT_ENTRIES 256 +#define GDT_SIZE (GDT_ENTRIES * 8) +#define GDT_ENTRY_TLS_ENTRIES 3 +#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8) + #endif diff --git a/include/asm-x86/segment_32.h b/include/asm-x86/segment_32.h index ff186e3..3e133ad 100644 --- a/include/asm-x86/segment_32.h +++ b/include/asm-x86/segment_32.h @@ -45,12 +45,9 @@ * 30 - unused * 31 - TSS for double fault handler */ -#define GDT_ENTRY_TLS_ENTRIES 3 #define GDT_ENTRY_TLS_MIN 6 #define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1) -#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8) - #define GDT_ENTRY_DEFAULT_USER_CS 14 #define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS * 8 + 3) @@ -87,7 +84,6 @@ * The GDT has 32 entries */ #define GDT_ENTRIES 32 -#define GDT_SIZE (GDT_ENTRIES * 8) /* Simple and small GDT entries for booting only */ @@ -112,24 +108,6 @@ #define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2 * 8) /* another data segment */ /* - * The interrupt descriptor table has room for 256 idt's, - * the global descriptor table is dependent on the number - * of tasks we can have.. - */ -#define IDT_ENTRIES 256 - -/* Bottom two bits of selector give the ring privilege level */ -#define SEGMENT_RPL_MASK 0x3 -/* Bit 2 is table indicator (LDT/GDT) */ -#define SEGMENT_TI_MASK 0x4 - -/* User mode is privilege level 3 */ -#define USER_RPL 0x3 -/* LDT segment has TI set, GDT has it cleared */ -#define SEGMENT_LDT 0x4 -#define SEGMENT_GDT 0x0 - -/* * Matching rules for certain types of segments. */ diff --git a/include/asm-x86/segment_64.h b/include/asm-x86/segment_64.h index dce7421..5cc7deb 100644 --- a/include/asm-x86/segment_64.h +++ b/include/asm-x86/segment_64.h @@ -33,8 +33,6 @@ #define GDT_ENTRY_TLS_MIN 12 #define GDT_ENTRY_TLS_MAX 14 -#define GDT_ENTRY_TLS_ENTRIES 3 - #define GDT_ENTRY_PER_CPU 15 /* Abused to load per CPU data from limit */ #define __PER_CPU_SEG (GDT_ENTRY_PER_CPU * 8 + 3) @@ -45,20 +43,5 @@ #define GS_TLS_SEL ((GDT_ENTRY_TLS_MIN+GS_TLS)*8 + 3) #define FS_TLS_SEL ((GDT_ENTRY_TLS_MIN+FS_TLS)*8 + 3) -#define IDT_ENTRIES 256 #define GDT_ENTRIES 16 -#define GDT_SIZE (GDT_ENTRIES * 8) -#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8) - -/* Bottom two bits of selector give the ring privilege level */ -#define SEGMENT_RPL_MASK 0x3 -/* Bit 2 is table indicator (LDT/GDT) */ -#define SEGMENT_TI_MASK 0x4 - -/* User mode is privilege level 3 */ -#define USER_RPL 0x3 -/* LDT segment has TI set, GDT has it cleared */ -#define SEGMENT_LDT 0x4 -#define SEGMENT_GDT 0x0 - #endif -- 1.4.4.2 _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linux-foundation.org/mailman/listinfo/virtualization
