Nakajima, Jun wrote:
> To me such atomicity is provided by the "sti" instruction (i.e. the
> processor begins responding to external, maskable interrupts _after_ the
> next instruction is executed), and there is nothing special with that
> combination "sti; hlt" (you can also have like "sti; ret", for example).
>
Sure, but there's no particular value in "sti; ret". While the sti mask
window works everywhere, its only cases like "sti; hlt" where it's
needed to avoid a race condition.
> So if you define a PV ops like STI(next_instruction), "safe_halt" for
> the native should be defined as STI("hlt"), and inlined as "sti; hlt".
>
That's only meaningful if the pv_op is implemented directly in x86
instructions - ie, the native (or almost native) case.
> If it's hard or we don't need to expose the semantics of "sti" other
> than that, I think it's okay to have a PV operation for safe_halt.
>
Yeah, the general form would be hard to support for a hypervisor. Xen,
for example, has an "atomically enable events and block" operation, but
no other "atomically enable events and do X" operations.
J
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