H. Peter Anvin wrote: > Zachary Amsden wrote: >> Some PTE optimizations for native and paravirt-ops kernels; this >> provides a huge win for shadow mode hypervisors and gets rid of >> some unnecessary atomic instructions in native kernels, saving >> even more on UP by getting rid of implicit LOCK on xchg instruction. > > You do know that P6 and higher don't do locked bus references as long > as the value is in the cache, right? Yes. Even then, last time I clocked instructions, xchg was still slower than read / write, although I could be misremembering. And it's not totally clear that they will always be in cached state, however, and for SMP, we still want to drop the implicit lock in cases where the processor might not know they are cached exclusive, but we know there are no other racing users. And there are plenty of old processors out there to still make it worthwhile. Zach _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linux-foundation.org/mailman/listinfo/virtualization
