On 8/11/06 8:18 pm, "Jeremy Fitzhardinge" <jeremy at goop.org> wrote: >> Do you mean the tlb entry gets invalidated as part of raising the >> fault? >> > > Specifically, does it simply invalidate the TLB at that point, or does > it re-walk the page table and populate it with the new PTE? It invalidates the TLB entry, to avoid a fault loop, but it will then #PF rather than walk the page tables in hardware. I believe this is to speed up the fairly common CoW fault path. I don't know whether it is actually documented anywhere: the x86 'architecture' seems to be defined by the behaviour of the various hardware implementations. I discovered this particular factoid from talking to one of the Intel hardware guys. Another factoid I discovered at the same meeting is that the CPU may cache partial page walks. So, for example, just because you 'detach' a page table from a page-directory entry, doesn't mean that page table won't be accessed on future hardware TLB fills. I confirmed both these factoids by constructing simple test cases: IIRC both AMD and Intel CPUs exhibit both behaviours. -- Keir
