Re: [PATCH] xhci: fix write to USB3_PSSEN and XUSB2PRM pci config registers

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On Mon, Sep 23, 2013 at 02:49:07PM -0700, Greg KH wrote:
> On Mon, Sep 23, 2013 at 04:38:22PM -0500, Bjorn Helgaas wrote:
> > On Mon, Sep 23, 2013 at 3:49 PM, Greg KH <greg@xxxxxxxxx> wrote:
> > > On Mon, Sep 23, 2013 at 09:06:54PM +0300, Xenia Ragiadakou wrote:
> > >> I had in mind that the pci_ops .read and .write defined by the PCI
> > >> driver will take care of consistent byteorder access to the
> > >> configuration registers. At least, that was what i understood after
> > >> reading the
> > >> chapter on PCI of Linux Device Drivers (more specifically for
> > >> pci_write_config_* functions, it states that "The word and dword
> > >> functions convert the value to little-endian before writing to the
> > >> peripheral device.").
> > >
> > > Hm, I wrote that paragraph (or at least I think I did), but I sure
> > > didn't remember this at all...
> > >
> > > Hm, wait, I do see this happening for the PowerPC cell PCI code, so it
> > > might happen somewhere burried in the platform-specific code for
> > > different arches.  You will not see it happen on x86 as there's no need
> > > to swap any bytes around.
> > 
> > Greg, with regard to Xenia's patch, is this an ack or a nack?  Since
> > you didn't include an "Acked-by" line, I assume you think Xenia's
> > patch is unnecessary.  In that case, is there any way to shut sparse
> > up so it doesn't complain about this?
> 
> At this point in time, I don't remember what the original patch looked
> like, and as it's an xhci patch, Sarah needs to ack it, not me :)

Greg: So you're saying that there isn't a need to convert values from
CPU byte-ordering to little endian byte-ordering before passing them on
to pci_write_config_*?

If so, then yes, Xenia's patch is fine and I'll pull that into my xHCI
tree.

Sarah Sharp
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