On Thursday 01 August 2013 02:34 AM, Stephen Warren wrote:
On 07/31/2013 11:42 AM, Tuomas Tynkkynen wrote:
The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
Peter, Prashant,
I think you said that the lock bits should work on Tegra30 (albeit they
don't on Tegra20)? Can you remind me if the do/don't?
If Peter and Prashant are OK with this patch, feel free to take my ack.
Hi Tuomas,
Sorry for the delayed response. Please make sure that avdd_usb_pll
regulator is enabled before enabling PLLU and utmip parameters are
configured properly.
If this this regulator is not enabled then you will get this kind of
timeout when enabling PLLU.
Thanks,
Prashant
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