Re: [PATCH] staging: dwc2: add driver parameter to set AHB config register value

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Hey Paul,

> > > diff --git a/drivers/staging/dwc2/core.h b/drivers/staging/dwc2/core.h
> > > index fc075a7..e771e40 100644
> > > --- a/drivers/staging/dwc2/core.h
> > > +++ b/drivers/staging/dwc2/core.h
> > > @@ -150,10 +150,11 @@ enum dwc2_lx_state {
> > >   *                      are enabled
> > >   * @reload_ctl:         True to allow dynamic reloading of HFIR register during
> > >   *                      runtime
> > > - * @ahb_single:         This bit enables SINGLE transfers for remainder data in
> > > - *                      a transfer for DMA mode of operation.
> > > - *                       0 - remainder data will be sent using INCR burst size
> > > - *                       1 - remainder data will be sent using SINGLE burst size
> > > + * @ahbcfg:             This field allows the default value of the GAHBCFG
> > > + *                      register to be overridden
> > > + *                       -1         - GAHBCFG value will not be overridden
> > > + *                       all others - GAHBCFG value will be overridden with
> > > + *                                    this value
> > >   * @otg_ver:            OTG version supported
> > >   *                       0 - 1.3
> > >   *                       1 - 2.0
> > Shouldn't this mention that a few of the bits in the register cannot be
> > set like this?
> 
> I could have added a comment along the lines of "see the HSOTG databook
> for valid values for this register". But e.g. the value used by the
> Broadcom SOC is not documented in the Synopsys databook. I'm guessing
> they made some enhancement to our core. So I don't even know what bits
> cannot be set in this register.

With "cannot be set", I meant the bits that are masked out by the driver
code (e.g., GAHBCFG_CTRL_MASK). I'll add a remark along those lines to
my "improve comments" patch I have queued, since your patch is already
picked up by Greg.

Gr.

Matthijs
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