Incompleteness of HW capability registers (Was: [PATCH] staging: dwc2: fix thinko in dwc2_hc_set_even_odd_frame())

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Hi Stephen,

> > I'm not sure how many of the below driver parameters are actually
> > required. I think as least the three fifo size parameters, plus
> > max_transfer_size and max_packet_count, are needed.
>
> I'm curious why any of them are required; why aren't the values embedded
> in the HW registers correct?

As far as I've understood, there are some values (mostly PHY related)
which cannot be detected from the HW registers. My interpretation is
that the HW registers only store parameters used to synthesize the core,
(i.e., I think they store if the core supports UTMI+ and/or ULPI PHYs,
but not what kind of PHY is actually attached).

Also IIUC, the FIFO size registers store the maximum values per FIFO and
a global maximum, but it could be that the sum of the individual maximum
FIFO sizes is more than the global maximum. This is something that could
be fixed in the driver though, by somehow "fairly" (or otherwise
intelligently) distributing the available FIFO memory over the various
FIFOs.

These are just the suspicions I have encountered while going through the
code, perhaps Paul can confirm them.

Gr.

Matthijs
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