Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

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On 5/31/2013 1:24 AM, Ruchika Kharwar wrote:
Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.
This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz

Signed-off-by: Ruchika Kharwar <ruchika@xxxxxx>
---
  drivers/usb/phy/phy-omap-usb3.c |    7 ++++++-
  1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
index a6e60b1..efe6e14 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/usb/phy/phy-omap-usb3.c
@@ -27,7 +27,7 @@
  #include <linux/delay.h>
  #include <linux/usb/omap_control_usb.h>
-#define NUM_SYS_CLKS 5
+#define	NUM_SYS_CLKS		6
  #define	PLL_STATUS		0x00000004
  #define	PLL_GO			0x00000008
  #define	PLL_CONFIGURATION1	0x0000000C
@@ -62,6 +62,7 @@ enum sys_clk_rate {
  	CLK_RATE_12MHZ,
  	CLK_RATE_16MHZ,
  	CLK_RATE_19MHZ,
+	CLK_RATE_20MHZ,
  	CLK_RATE_26MHZ,
  	CLK_RATE_38MHZ
  };
@@ -72,6 +73,8 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
  	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
  	{1250, 12, 4, 20, 0},		/* 26 MHz */
  	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
+	{1000, 7, 4, 10, 0},            /* 20 MHz */
+
  };

CLK_RATE_20MHZ is 3 but 20MHz value added in array at offset 5???

  static int omap_usb3_suspend(struct usb_phy *x, int suspend)
@@ -122,6 +125,8 @@ static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
  		return CLK_RATE_16MHZ;
  	case 19200000:
  		return CLK_RATE_19MHZ;
+	case 20000000:
+		return CLK_RATE_20MHZ;
  	case 26000000:
  		return CLK_RATE_26MHZ;
  	case 38400000:

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