From: supriya karanth <supriya.karanth@xxxxxxxxxxxxxx>
Added pause, resume, tx_status and check_status functions
Signed-off-by: Supriya Karanth <supriya.karanth@xxxxxxxxxxxxxx>
Signed-off-by: Praveena NADAHALLY <praveen.nadahally@xxxxxxxxxxxxxx>
Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
---
drivers/usb/musb/musbhsdma.c | 72 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 3d1fd52..c5714b9 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -246,6 +246,74 @@ static int dma_channel_abort(struct dma_channel *channel)
return 0;
}
+static int dma_channel_pause(struct dma_channel *channel)
+{
+ /*
+ * Probably nothing to be done here. This is needed
+ * only for certain DMA controllers which require
+ * the DMA channel to be paused to get correct DMA
+ * transfer residue
+ */
+ return 0;
+}
+
+static int dma_channel_resume(struct dma_channel *channel)
+{
+ /* Probably nothing to be done here */
+ return 0;
+}
+
+static int dma_channel_tx_status(struct dma_channel *channel)
+{
+ struct musb_dma_channel *musb_channel = channel->private_data;
+ void __iomem *mbase = musb_channel->controller->base;
+
+ u8 bchannel = musb_channel->idx;
+ u32 addr, count, residue;
+
+ /*
+ * Get the number of bytes left to be transferred over
+ * DMA
+ * The MUSB spec mentions "The DMA controller ADDR register
+ * will have been incremented as packets were unloaded from
+ * the fifo, the processor can determine the size of the
+ * transfer by comparing the current value of ADDR against
+ * the start address of the memory buffer
+ */
+ /* residue = musb_read_hsdma_count(mbase, bchannel); */
+ addr = musb_read_hsdma_addr(mbase, bchannel);
+ count = addr - musb_channel->start_addr;
+ residue = channel->prog_len - count;
+
+ return residue;
+}
+
+static int dma_channel_check_residue(struct dma_channel *channel, u32 residue)
+{
+ int status;
+
+ /* In cases where we know the transfer length and were expecting
+ * a DMA completion we could get into the DMA busy condition
+ * here if the next packet is short and the EP interrupt occurs
+ * before we recieve dma_completion interrupt for current transfer
+ * Wait for dma_completion. MUSB will interrupt us again for this
+ * short packet when we clear the DMA bits
+ */
+ if (!residue) {
+ /* Wait for DMA completion */
+ status = -EINPROGRESS;
+ } else if (residue == channel->prog_len) {
+ /* Nothing transferred over DMA? */
+ WARN_ON(1);
+ status = -EINVAL;
+ } else {
+ /* residue looks OK */
+ status = 0;
+ }
+
+ return status;
+}
+
static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
struct musb_dma_controller *controller = private_data;
@@ -406,6 +474,10 @@ struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *ba
controller->controller.channel_release = dma_channel_release;
controller->controller.channel_program = dma_channel_program;
controller->controller.channel_abort = dma_channel_abort;
+ controller->controller.channel_pause = dma_channel_pause;
+ controller->controller.channel_resume = dma_channel_resume;
+ controller->controller.tx_status = dma_channel_tx_status;
+ controller->controller.check_residue = dma_channel_check_residue;
if (request_irq(irq, dma_controller_irq, 0,
dev_name(musb->controller), &controller->controller)) {
--
1.7.1
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