On Thu, Jan 17, 2013 at 10:21:53AM -0500, Alan Stern wrote: > On Thu, 17 Jan 2013, Felipe Balbi wrote: > > > > Bits 31 & 30 from PORTSC register were allocated by our SOC designers > > > to inform the host controller about the PHY type to be used. > > > > Wow, that's something you should never do. PORTSC register belongs to > > the EHCI controller and those bits are reserved for future use and they > > *MUST* return zero. I wouldn't be surprised if current EHCI driver > > assumes those bits will be zero and/or makes sure they're set to zero > > when writing to PORTSC register. > > In fact, those bits _have_ been assigned an official purpose in the > EHCI-1.1 addendum. Presumably the Tegra hardware only supports > EHCI-1.0. I see, they're used for device addresses now. How can we make sure on Tegra systems we won't use those top two bits ? -- balbi
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