On Mon, 30 Jul 2012, Alexey Filin wrote: > > Yes, something like it might work, I think. But you probably wouldn't > > want to use URBs for this; they have too much overhead. You'd need a > > more direct interface to the host controller driver. > > really, too much, about 7 us on my pc (Core2 Duo CPU E7500 2.93GHz) > a direct access to EHCI controller should be used > > > > > The EHCI spec doesn't put any strict time limit on how long the host > > controller can wait before writing back the completion information to a > > transfer descriptor. If the hardware waits more than 1 us, your scheme > > is doomed. > > it works on Intel Corporation N10/ICH 7 Family USB2 EHCI Controller > > I measured times for 4-byte IN transfer: > > fill+submit time 7 us (average) +- 1.5 us > transaction time 3.7 us (average) +- 0.5 us (without tails) How did you measure the transaction time? Using a bus analyzer? > completion time 20-150 us (flat), as expected for microframe boundary > not synched with transfer > > getnstimeofday overhead 60 ns (used to measure times) > > transaction time increases up to 20 us for 1% of 10000 transfers > > histograms in png are attached to the email. > > so 4 us latency is achievable For one transaction. If each external read/write operation requires two USB transactions then the latency will be higher. But maybe you could change the implementation: Map an external bus read to a USB IN transfer and an external bus write to a USB OUT transfer. Alan Stern -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
