Hi, On Thu, Mar 22, 2012 at 06:28:26PM +0000, Paul Zimmerman wrote: > > > > context, toggle clocks, set pads in safe mode (when needed) and so on. > > > > > > > > But fair enough, both ways would work fine. > > > > > > I would also recommend your/Alan's approach to this over Felipe's way. > > > We have a DWC3 platform with an (admittedly oddball) PM implementation > > > that requires the bus driver to have some knowledge of the base driver's > > > internal state, and needs the two drivers to be able to communicate with > > > each other. With the base driver being a separate platform device, this > > > is nearly impossible to achieve in a clean way. If the DWC3 driver was > > > designed the way you and Alan are recommending, it would be easy. > > > > > > I'm trying to convince Felipe to change the DWC3 driver design to > > > accommodate this, but I hold out little hope for that :) > > > > yeah, I'm not thinking on taking that patch, sorry. Didn't you say SNPS > > had agreed on rebuilding the FPGA system so that it's a more standard > > PCIe implementation ? > > > > I still owe you another possible implementation for the whole PM thing, > > sorry about the delay. > > Dropped the other folks from CC since they probably aren't interested. > > The FPGA rework is very low priority, those guys have more important > stuff to work on at the moment. Plus management doesn't understand > why the current design won't work, since the Synopsys driver supports > it OK. > > So I'm not sure when the FPGA rework will happen. Ok, so let's work with what we have now. I'll try to shuffle your patches around to the way I think they could/should be done, but I'll need your help testing since I don't have any hibernation-enabled version of the IP at hand. Hope it's ok with you ;-) -- balbi
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