Hi,
On Wed, Mar 21, 2012 at 5:29 PM, Lukasz Majewski <l.majewski@xxxxxxxxxxx> wrote:
> From: Joonyoung Shim <jy0922.shim@xxxxxxxxxxx>
>
> The s3c-hsotg driver controls S3C64XX specific registers directly but
> this driver can be to EXYNOS also. This removes arch specific parts from
> driver using platform data callbacks.
>
> Signed-off-by: Joonyoung Shim <jy0922.shim@xxxxxxxxxxx>
> Signed-off-by: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
> ---
> drivers/usb/gadget/s3c-hsotg.c | 94 ++++++----------------------------------
> 1 files changed, 14 insertions(+), 80 deletions(-)
Shouldn't this file actually be in drivers/usb/otg/ ??
>
> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
> index 69295ba..6dab16a 100644
> --- a/drivers/usb/gadget/s3c-hsotg.c
> +++ b/drivers/usb/gadget/s3c-hsotg.c
> @@ -35,9 +35,9 @@
>
> #include <plat/regs-usb-hsotg-phy.h>
> #include <plat/regs-usb-hsotg.h>
> -#include <mach/regs-sys.h>
> #include <plat/udc-hs.h>
> #include <plat/cpu.h>
> +#include <plat/usb-phy.h>
>
> #define DMA_ADDR_INVALID (~((dma_addr_t)0))
>
> @@ -2843,51 +2843,6 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
> }
> }
>
> -/**
> - * s3c_hsotg_otgreset - reset the OtG phy block
> - * @hsotg: The host state.
> - *
> - * Power up the phy, set the basic configuration and start the PHY.
> - */
> -static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
> -{
> - struct clk *xusbxti;
> - u32 pwr, osc;
> -
> - pwr = readl(S3C_PHYPWR);
> - pwr &= ~0x19;
> - writel(pwr, S3C_PHYPWR);
> - mdelay(1);
> -
> - osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
> -
> - xusbxti = clk_get(hsotg->dev, "xusbxti");
> - if (xusbxti && !IS_ERR(xusbxti)) {
> - switch (clk_get_rate(xusbxti)) {
> - case 12*MHZ:
> - osc |= S3C_PHYCLK_CLKSEL_12M;
> - break;
> - case 24*MHZ:
> - osc |= S3C_PHYCLK_CLKSEL_24M;
> - break;
> - default:
> - case 48*MHZ:
> - /* default reference clock */
> - break;
> - }
> - clk_put(xusbxti);
> - }
> -
> - writel(osc | 0x10, S3C_PHYCLK);
> -
> - /* issue a full set of resets to the otg and core */
> -
> - writel(S3C_RSTCON_PHY, S3C_RSTCON);
> - udelay(20); /* at-least 10uS */
> - writel(0, S3C_RSTCON);
> -}
> -
> -
> static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
> {
> u32 cfg4;
> @@ -3260,34 +3215,6 @@ static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
> debugfs_remove(hsotg->debug_root);
> }
>
> -/**
> - * s3c_hsotg_gate - set the hardware gate for the block
> - * @pdev: The device we bound to
> - * @on: On or off.
> - *
> - * Set the hardware gate setting into the block. If we end up on
> - * something other than an S3C64XX, then we might need to change this
> - * to using a platform data callback, or some other mechanism.
> - */
> -static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
> -{
> - unsigned long flags;
> - u32 others;
> -
> - local_irq_save(flags);
> -
> - others = __raw_readl(S3C64XX_OTHERS);
> - if (on)
> - others |= S3C64XX_OTHERS_USBMASK;
> - else
> - others &= ~S3C64XX_OTHERS_USBMASK;
> - __raw_writel(others, S3C64XX_OTHERS);
> -
> - local_irq_restore(flags);
> -}
> -
> -static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
> -
> static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
> {
> struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
> @@ -3297,8 +3224,11 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
> int epnum;
> int ret;
>
> - if (!plat)
> - plat = &s3c_hsotg_default_pdata;
> + plat = pdev->dev.platform_data;
The first line after probe already does this initialization
Thanks
Kishon
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