Re: [PATCH v5] usb: fsl_udc_core: prime status stage once data stage has primed

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On Wed, Feb 29, 2012 at 08:19:46PM +0800, Peter Chen wrote:
> - For Control Read transfer, the ACK handshake on an IN transaction
> may be corrupted, so the device may not receive the ACK for data
> stage, the complete irq will not occur at this situation.
> Therefore, we need to move prime status stage from complete irq
> routine to the place where the data stage has just primed, or the
> host will never get ACK for status stage.
> The above issue has been described at USB2.0 spec chapter 8.5.3.3.
> 
> - After adding prime status stage just after prime the data stage,
> there is a potential problem when the status dTD is added before the data stage
> has primed by hardware. The reason is the device's dTD descriptor has NO direction bit,
> if data stage (IN) prime hasn't finished, the status stage(OUT)
> dTD will be added at data stage dTD's Next dTD Pointer, so when the data stage
> transfer has finished, the status dTD will be primed as IN by hardware,
> then the host will never receive ACK from the device side for status stage.
> 
> - Delete below code at fsl_ep_queue:
>        /* Update ep0 state */
>        if ((ep_index(ep) == 0))
>                udc->ep0_state = DATA_STATE_XMIT;
> the udc->ep0_state will be updated again after udc->driver->setup
> finishes.
> 
> It is tested at i.mx51 bbg board with g_mass_storage, g_ether, g_serial.
> 
> Signed-off-by: Peter Chen <peter.chen@xxxxxxxxxxxxx>

applied, thanks

-- 
balbi

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