PS3 EHCI HC errata fix 316 - The PS3 EHCI HC will reset its
internal INSNREGXX setup regs back to the chip default values
on Host Controller Reset (CMD_RESET) or Light Host Controller
Reset (CMD_LRESET). The work-around for this is for the HC
driver to re-initialise these regs when ever the HC is reset.
Signed-off-by: Geoff Levand <geoff@xxxxxxxxxxxxx>
---
drivers/usb/host/ehci-ps3.c | 34 ++++++++++++++++++++++++++++++++++
1 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c
index b173d94..11f1f42ee 100644
--- a/drivers/usb/host/ehci-ps3.c
+++ b/drivers/usb/host/ehci-ps3.c
@@ -21,6 +21,38 @@
#include <asm/firmware.h>
#include <asm/ps3.h>
+/**
+ * enum ps3_ehci_hc_insnreg - PS3 HC internal setup register offsets.
+ *
+ * Offsets in bytes from the EHCI operational regs (ehci->regs).
+ **/
+
+enum ps3_ehci_hc_insnreg {
+ ps3_ehci_hc_insnreg01 = 0x084,
+ ps3_ehci_hc_insnreg02 = 0x088,
+ ps3_ehci_hc_insnreg03 = 0x08c,
+};
+
+static void ps3_ehci_post_reset(struct ehci_hcd *ehci)
+{
+ /* PS3 EHCI HC errata fix 316 - The PS3 EHCI HC will reset its
+ * internal INSNREGXX setup regs back to the chip default values
+ * on Host Controller Reset (CMD_RESET) or Light Host Controller
+ * Reset (CMD_LRESET). The work-around for this is for the HC
+ * driver to re-initialise these regs when ever the HC is reset.
+ */
+
+ /* Set burst transfer counts to 256 out, 32 in. */
+
+ writel_be(0x01000020, (void __iomem *)ehci->regs +
+ ps3_ehci_hc_insnreg01);
+
+ /* Enable burst transfer counts. */
+
+ writel_be(0x00000001, (void __iomem *)ehci->regs +
+ ps3_ehci_hc_insnreg03);
+}
+
static int ps3_ehci_hc_reset(struct usb_hcd *hcd)
{
int result;
@@ -32,6 +64,8 @@ static int ps3_ehci_hc_reset(struct usb_hcd *hcd)
ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci,
&ehci->caps->hc_capbase));
+ ehci->post_reset = ps3_ehci_post_reset;
+
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
--
1.7.4.1
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