Add internal UTMI PHY support for P5020/P3041/P101x platforms
for both USB Host and Peripheral modes
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@xxxxxxxxxxxxx>
Signed-off-by: Roy Zang <tie-fei.zang@xxxxxxxxxxxxx>
---
Changes for v2:
- replaced udelay() with mdelay()
drivers/usb/gadget/fsl_udc_core.c | 12 ++++++++++++
drivers/usb/gadget/fsl_usb2_udc.h | 4 ++++
drivers/usb/host/ehci-fsl.c | 17 ++++++++++++++++-
drivers/usb/host/ehci-fsl.h | 13 ++++++++++++-
4 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 2cd9a60..8038d88 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -250,6 +250,18 @@ static int dr_controller_setup(struct fsl_udc *udc)
portctrl |= PORTSCX_PTW_16BIT;
/* fall through */
case FSL_USB2_PHY_UTMI:
+#if defined(CONFIG_FSL_SOC_BOOKE)
+ setbits32(&usb_sys_regs->control, USB_CTRL_UTMI_PHY_EN |
+ USB_CTRL_USB_EN);
+ /* UTMI PLY clk becomes stable after 10ms */
+ mdelay(10);
+ /* check for PHY clk */
+ if (!(fsl_readl(&usb_sys_regs->control) &
+ USB_CTRL_PHY_CLK_VLD)) {
+ ERR("usb phy clk not found\n");
+ return -EFAULT;
+ }
+#endif
portctrl |= PORTSCX_PTS_UTMI;
break;
case FSL_USB2_PHY_SERIAL:
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index 1d51be8..b955eec 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -1,4 +1,5 @@
/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
* Freescale USB device/endpoint management registers
*/
#ifndef __FSL_USB2_UDC_H
@@ -348,6 +349,9 @@ struct usb_sys_interface {
/* control Register Bit Masks */
#define USB_CTRL_IOENB 0x00000004
#define USB_CTRL_ULPI_INT0EN 0x00000001
+#define USB_CTRL_UTMI_PHY_EN 0x00000200
+#define USB_CTRL_USB_EN 0x00000004
+#define USB_CTRL_PHY_CLK_VLD 0x00020000
/* Endpoint Queue Head data struct
* Rem: all the variables of qh are LittleEndian Mode
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index f380bf9..649c023 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -1,6 +1,6 @@
/*
* Copyright 2005-2009 MontaVista Software, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -215,6 +215,10 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
enum fsl_usb2_phy_modes phy_mode,
unsigned int port_offset)
{
+#if defined(CONFIG_FSL_SOC_BOOKE)
+ struct usb_hcd *hcd = ehci_to_hcd(ehci);
+ void __iomem *non_ehci = hcd->regs;
+#endif
u32 portsc;
portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
@@ -231,6 +235,17 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+#if defined(CONFIG_FSL_SOC_BOOKE)
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN |
+ USB_CTRL_USB_EN);
+ /* UTMI PLY clk becomes stable after 10ms */
+ mdelay(10);
+ /* check for PHY clk */
+ if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VLD)) {
+ printk(KERN_ERR"usb phy clk not found\n");
+ return;
+ }
+#endif
portsc |= PORT_PTS_UTMI;
break;
case FSL_USB2_PHY_NONE:
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 4918062..cdf1b47 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc.
+/* Copyright (C) 2005-2011 Freescale Semiconductor, Inc.
* Copyright (c) 2005 MontaVista Software
*
* This program is free software; you can redistribute it and/or modify it
@@ -46,4 +46,15 @@
#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
#define SNOOP_SIZE_2GB 0x1e
+
+/* control Register Bit Masks */
+#define ULPI_INT_EN (1<<0)
+#define WU_INT_EN (1<<1)
+#define USB_CTRL_USB_EN (1<<2)
+#define LINE_STATE_FILTER__EN (1<<3)
+#define KEEP_OTG_ON (1<<4)
+#define OTG_PORT (1<<5)
+#define PLL_RESET (1<<8)
+#define UTMI_PHY_EN (1<<9)
+#define PHY_CLK_VLD (1<<17)
#endif /* _EHCI_FSL_H */
--
1.6.1
--
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