Re: [PATCH V2 4/4] USB: UHCI: Support big endian GRUSBHC HC

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On 09/05/11 22:37, Alan Stern wrote:
> On Mon, 9 May 2011, Jan Andersson wrote:
> 
>> This patch adds support for big endian GRUSBHC UHCI controllers.
>> The HCD bus glue will probe the register interface to determine
>> the endianness of the controller.
>>
>> Tested on GR-LEON4-ITX board which has a controller with little endian
>> interface and on custom LEON3 board with a BE controller.
> 
> ...
> 
>> diff --git a/drivers/usb/host/uhci-hcd.h b/drivers/usb/host/uhci-hcd.h
>> index 22a4ce6..079fac3 100644
>> --- a/drivers/usb/host/uhci-hcd.h
>> +++ b/drivers/usb/host/uhci-hcd.h
>> @@ -545,9 +545,18 @@ static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
>>  #if defined(CONFIG_USB_UHCI_BIG_ENDIAN_MMIO)
>>  /* Support (non-PCI) big endian host controllers */
>>  #define uhci_big_endian_mmio(u)		((u)->big_endian_mmio)
>> +/* Arch-specific big endian read/write functions */
>> +#if defined(CONFIG_SPARC_LEON)
>> +#define readl_be(addr)		__raw_readl(addr)
>> +#define writel_be(val, addr)	__raw_writel(val, addr)
>> +#define readw_be(addr)		__raw_readw(addr)
>> +#define writew_be(val, addr)	__raw_writew(val, addr)
>> +#define readb_be(addr)		__raw_readb(addr)
>> +#define writeb_be(val, addr)	__raw_writeb(val, addr)
>> +#endif  /* CONFIG_SPARC_LEON */
> 
> Shouldn't these things already be defined in an arch-specific header 
> file?  Just like readl(), __raw_readl(), ... ?
> 

If there is call to make a big endian access that works on all
architectures that would be a better choice.

I could have used __raw_readl() directly but I didn't since the above is
what is done in ehci.h. IMHO it makes sense to have it like this because
(again assuming that read/write() always is defined to work with LE
memory) a read/write*_be is what we need to do and then people can
define the appropriate function/macro for their arch here locally.

(It is possible that I have missed or misunderstood how these io
routines are intended work, to me it seems like much has been based on
the assumption that I/O will always be connected over PCI or some other
LE bus).

I propose that the current solution is kept. If that is not acceptable I
suggest that the calls are changed to use the __raw versions of
read/write (but that could break in case the __raw versions are defined
to be native endian and someone wants to use a BE controller together
with a LE processor).

Also, thanks for your comments to patches 3 and 4, I will make changes
accordingly.

Best regards,
  Jan
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