Richard Retanubun wrote:
This patch moves the HcInterrupt register write to clear the
pending interrupt to after the isr work is done, doing this removes
glitches in the irq line.
Signed-off-by: Richard Retanubun <richardretanubun@xxxxxxxxxxxxx>
---
Hi Sebastian,
I found that moving the imask write after the work removes a 50ns
'glitch' that I saw on the INT line of the switch.
Just wondering if you have specific reasons to clear it right away.
Lets say you get an interrupt and ATL & INT is set. You do ATL. This takes
some time. You do INT. This takes some times. While serving INT the core
gets another ATL packet ready (a new one, not processed yet) and would
issue an Interrupt but it does not because it is still active. Once you
are done with INT you ack both ATL and INT but you did not serve the last
one ATL packet.
Thanks for your time
Richard
Sebastian
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