Hi,
grepping for tdi (arc/chipidea/mips otg ehci like controller) registers in driver/usb/gadget show interesting things : it seems we have 4 drivers for handling the same controller.
- fsl_udc_core [1]
- ci13xxx_udc [2]
- mv_udc [3]
- langwell [4]
fsl is the historic driver (freesale and tegra will be using it).
ci13xxx was added by mips and msm chip use it
mv_udc/langwell is newer.
I didn't look at the driver in details, there may be tiny difference between all this controllers.
Shouldn't we try to merge them and rename to a clear name in order people don't rewrite again the same driver ?
Matthieu
PS :
even if langwell is the only one to handle lpm, note that ci13xxx_udc also take care of if (hccparams/reg offset).
[1]
/* USB DR device mode registers (Little Endian) */
struct usb_dr_device {
/* Capability register */
u8 res1[256];
u16 caplength; /* Capability Register Length */
u16 hciversion; /* Host Controller Interface Version */
u32 hcsparams; /* Host Controller Structual Parameters */
u32 hccparams; /* Host Controller Capability Parameters */
u8 res2[20];
u32 dciversion; /* Device Controller Interface Version */
u32 dccparams; /* Device Controller Capability Parameters */
u8 res3[24];
/* Operation register */
u32 usbcmd; /* USB Command Register */
u32 usbsts; /* USB Status Register */
u32 usbintr; /* USB Interrupt Enable Register */
u32 frindex; /* Frame Index Register */
u8 res4[4];
u32 deviceaddr; /* Device Address */
u32 endpointlistaddr; /* Endpoint List Address Register */
u8 res5[4];
u32 burstsize; /* Master Interface Data Burst Size Register */
u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
u8 res6[24];
u32 configflag; /* Configure Flag Register */
u32 portsc1; /* Port 1 Status and Control Register */
u8 res7[28];
u32 otgsc; /* On-The-Go Status and Control */
u32 usbmode; /* USB Mode Register */
u32 endptsetupstat; /* Endpoint Setup Status Register */
u32 endpointprime; /* Endpoint Initialization Register */
u32 endptflush; /* Endpoint Flush Register */
u32 endptstatus; /* Endpoint Status Register */
u32 endptcomplete; /* Endpoint Complete Register */
u32 endptctrl[6]; /* Endpoint Control Registers */
};
/* USB DR host mode registers (Little Endian) */
struct usb_dr_host {
/* Capability register */
u8 res1[256];
u16 caplength; /* Capability Register Length */
u16 hciversion; /* Host Controller Interface Version */
u32 hcsparams; /* Host Controller Structual Parameters */
u32 hccparams; /* Host Controller Capability Parameters */
u8 res2[20];
u32 dciversion; /* Device Controller Interface Version */
u32 dccparams; /* Device Controller Capability Parameters */
u8 res3[24];
/* Operation register */
u32 usbcmd; /* USB Command Register */
u32 usbsts; /* USB Status Register */
u32 usbintr; /* USB Interrupt Enable Register */
u32 frindex; /* Frame Index Register */
u8 res4[4];
u32 periodiclistbase; /* Periodic Frame List Base Address Register */
u32 asynclistaddr; /* Current Asynchronous List Address Register */
u8 res5[4];
u32 burstsize; /* Master Interface Data Burst Size Register */
u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
u8 res6[24];
u32 configflag; /* Configure Flag Register */
u32 portsc1; /* Port 1 Status and Control Register */
u8 res7[28];
u32 otgsc; /* On-The-Go Status and Control */
u32 usbmode; /* USB Mode Register */
u32 endptsetupstat; /* Endpoint Setup Status Register */
u32 endpointprime; /* Endpoint Initialization Register */
u32 endptflush; /* Endpoint Flush Register */
u32 endptstatus; /* Endpoint Status Register */
u32 endptcomplete; /* Endpoint Complete Register */
u32 endptctrl[6]; /* Endpoint Control Registers */
};
/* non-EHCI USB system interface registers (Big Endian) */
struct usb_sys_interface {
u32 snoop1;
u32 snoop2;
u32 age_cnt_thresh; /* Age Count Threshold Register */
u32 pri_ctrl; /* Priority Control Register */
u32 si_ctrl; /* System Interface Control Register */
u8 res[236];
u32 control; /* General Purpose Control Register */
};
/* ep0 transfer state */
#define WAIT_FOR_SETUP 0
#define DATA_STATE_XMIT 1
#define DATA_STATE_NEED_ZLP 2
#define WAIT_FOR_OUT_STATUS 3
#define DATA_STATE_RECV 4
/* Device Controller Capability Parameter register */
#define DCCPARAMS_DC 0x00000080
#define DCCPARAMS_DEN_MASK 0x0000001f
/* Frame Index Register Bit Masks */
#define USB_FRINDEX_MASKS 0x3fff
/* USB CMD Register Bit Masks */
#define USB_CMD_RUN_STOP 0x00000001
#define USB_CMD_CTRL_RESET 0x00000002
#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
#define USB_CMD_INT_AA_DOORBELL 0x00000040
#define USB_CMD_ASP 0x00000300
#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800
#define USB_CMD_SUTW 0x00002000
#define USB_CMD_ATDTW 0x00004000
#define USB_CMD_ITC 0x00FF0000
/* bit 15,3,2 are frame list size */
#define USB_CMD_FRAME_SIZE_1024 0x00000000
#define USB_CMD_FRAME_SIZE_512 0x00000004
#define USB_CMD_FRAME_SIZE_256 0x00000008
#define USB_CMD_FRAME_SIZE_128 0x0000000C
#define USB_CMD_FRAME_SIZE_64 0x00008000
#define USB_CMD_FRAME_SIZE_32 0x00008004
#define USB_CMD_FRAME_SIZE_16 0x00008008
#define USB_CMD_FRAME_SIZE_8 0x0000800C
/* bit 9-8 are async schedule park mode count */
#define USB_CMD_ASP_00 0x00000000
#define USB_CMD_ASP_01 0x00000100
#define USB_CMD_ASP_10 0x00000200
#define USB_CMD_ASP_11 0x00000300
#define USB_CMD_ASP_BIT_POS 8
/* bit 23-16 are interrupt threshold control */
#define USB_CMD_ITC_NO_THRESHOLD 0x00000000
#define USB_CMD_ITC_1_MICRO_FRM 0x00010000
#define USB_CMD_ITC_2_MICRO_FRM 0x00020000
#define USB_CMD_ITC_4_MICRO_FRM 0x00040000
#define USB_CMD_ITC_8_MICRO_FRM 0x00080000
#define USB_CMD_ITC_16_MICRO_FRM 0x00100000
#define USB_CMD_ITC_32_MICRO_FRM 0x00200000
#define USB_CMD_ITC_64_MICRO_FRM 0x00400000
#define USB_CMD_ITC_BIT_POS 16
/* USB STS Register Bit Masks */
#define USB_STS_INT 0x00000001
#define USB_STS_ERR 0x00000002
#define USB_STS_PORT_CHANGE 0x00000004
#define USB_STS_FRM_LST_ROLL 0x00000008
#define USB_STS_SYS_ERR 0x00000010
#define USB_STS_IAA 0x00000020
#define USB_STS_RESET 0x00000040
#define USB_STS_SOF 0x00000080
#define USB_STS_SUSPEND 0x00000100
#define USB_STS_HC_HALTED 0x00001000
#define USB_STS_RCL 0x00002000
#define USB_STS_PERIODIC_SCHEDULE 0x00004000
#define USB_STS_ASYNC_SCHEDULE 0x00008000
/* USB INTR Register Bit Masks */
#define USB_INTR_INT_EN 0x00000001
#define USB_INTR_ERR_INT_EN 0x00000002
#define USB_INTR_PTC_DETECT_EN 0x00000004
#define USB_INTR_FRM_LST_ROLL_EN 0x00000008
#define USB_INTR_SYS_ERR_EN 0x00000010
#define USB_INTR_ASYN_ADV_EN 0x00000020
#define USB_INTR_RESET_EN 0x00000040
#define USB_INTR_SOF_EN 0x00000080
#define USB_INTR_DEVICE_SUSPEND 0x00000100
/* Device Address bit masks */
#define USB_DEVICE_ADDRESS_MASK 0xFE000000
#define USB_DEVICE_ADDRESS_BIT_POS 25
/* endpoint list address bit masks */
#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
/* PORTSCX Register Bit Masks */
#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001
#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002
#define PORTSCX_PORT_ENABLE 0x00000004
#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008
#define PORTSCX_OVER_CURRENT_ACT 0x00000010
#define PORTSCX_OVER_CURRENT_CHG 0x00000020
#define PORTSCX_PORT_FORCE_RESUME 0x00000040
#define PORTSCX_PORT_SUSPEND 0x00000080
#define PORTSCX_PORT_RESET 0x00000100
#define PORTSCX_LINE_STATUS_BITS 0x00000C00
#define PORTSCX_PORT_POWER 0x00001000
#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000
#define PORTSCX_PORT_TEST_CTRL 0x000F0000
#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000
#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000
#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000
#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000
#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000
#define PORTSCX_PORT_SPEED_MASK 0x0C000000
#define PORTSCX_PORT_WIDTH 0x10000000
#define PORTSCX_PHY_TYPE_SEL 0xC0000000
/* bit 11-10 are line status */
#define PORTSCX_LINE_STATUS_SE0 0x00000000
#define PORTSCX_LINE_STATUS_JSTATE 0x00000400
#define PORTSCX_LINE_STATUS_KSTATE 0x00000800
#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00
#define PORTSCX_LINE_STATUS_BIT_POS 10
/* bit 15-14 are port indicator control */
#define PORTSCX_PIC_OFF 0x00000000
#define PORTSCX_PIC_AMBER 0x00004000
#define PORTSCX_PIC_GREEN 0x00008000
#define PORTSCX_PIC_UNDEF 0x0000C000
#define PORTSCX_PIC_BIT_POS 14
/* bit 19-16 are port test control */
#define PORTSCX_PTC_DISABLE 0x00000000
#define PORTSCX_PTC_JSTATE 0x00010000
#define PORTSCX_PTC_KSTATE 0x00020000
#define PORTSCX_PTC_SEQNAK 0x00030000
#define PORTSCX_PTC_PACKET 0x00040000
#define PORTSCX_PTC_FORCE_EN 0x00050000
#define PORTSCX_PTC_BIT_POS 16
/* bit 27-26 are port speed */
#define PORTSCX_PORT_SPEED_FULL 0x00000000
#define PORTSCX_PORT_SPEED_LOW 0x04000000
#define PORTSCX_PORT_SPEED_HIGH 0x08000000
#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000
#define PORTSCX_SPEED_BIT_POS 26
/* bit 28 is parallel transceiver width for UTMI interface */
#define PORTSCX_PTW 0x10000000
#define PORTSCX_PTW_8BIT 0x00000000
#define PORTSCX_PTW_16BIT 0x10000000
/* bit 31-30 are port transceiver select */
#define PORTSCX_PTS_UTMI 0x00000000
#define PORTSCX_PTS_ULPI 0x80000000
#define PORTSCX_PTS_FSLS 0xC0000000
#define PORTSCX_PTS_BIT_POS 30
/* otgsc Register Bit Masks */
#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
#define OTGSC_CTRL_OTG_TERM 0x00000008
#define OTGSC_CTRL_DATA_PULSING 0x00000010
#define OTGSC_STS_USB_ID 0x00000100
#define OTGSC_STS_A_VBUS_VALID 0x00000200
#define OTGSC_STS_A_SESSION_VALID 0x00000400
#define OTGSC_STS_B_SESSION_VALID 0x00000800
#define OTGSC_STS_B_SESSION_END 0x00001000
#define OTGSC_STS_1MS_TOGGLE 0x00002000
#define OTGSC_STS_DATA_PULSING 0x00004000
#define OTGSC_INTSTS_USB_ID 0x00010000
#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
#define OTGSC_INTSTS_B_SESSION_END 0x00100000
#define OTGSC_INTSTS_1MS 0x00200000
#define OTGSC_INTSTS_DATA_PULSING 0x00400000
#define OTGSC_INTR_USB_ID 0x01000000
#define OTGSC_INTR_A_VBUS_VALID 0x02000000
#define OTGSC_INTR_A_SESSION_VALID 0x04000000
#define OTGSC_INTR_B_SESSION_VALID 0x08000000
#define OTGSC_INTR_B_SESSION_END 0x10000000
#define OTGSC_INTR_1MS_TIMER 0x20000000
#define OTGSC_INTR_DATA_PULSING 0x40000000
/* USB MODE Register Bit Masks */
#define USB_MODE_CTRL_MODE_IDLE 0x00000000
#define USB_MODE_CTRL_MODE_DEVICE 0x00000002
#define USB_MODE_CTRL_MODE_HOST 0x00000003
#define USB_MODE_CTRL_MODE_RSV 0x00000001
#define USB_MODE_SETUP_LOCK_OFF 0x00000008
#define USB_MODE_STREAM_DISABLE 0x00000010
/* Endpoint Flush Register */
#define EPFLUSH_TX_OFFSET 0x00010000
#define EPFLUSH_RX_OFFSET 0x00000000
/* Endpoint Setup Status bit masks */
#define EP_SETUP_STATUS_MASK 0x0000003F
#define EP_SETUP_STATUS_EP0 0x00000001
/* ENDPOINTCTRLx Register Bit Masks */
#define EPCTRL_TX_ENABLE 0x00800000
#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
#define EPCTRL_TX_TYPE 0x000C0000
#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
#define EPCTRL_TX_EP_STALL 0x00010000
#define EPCTRL_RX_ENABLE 0x00000080
#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
#define EPCTRL_RX_TYPE 0x0000000C
#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
#define EPCTRL_RX_EP_STALL 0x00000001
/* bit 19-18 and 3-2 are endpoint type */
#define EPCTRL_EP_TYPE_CONTROL 0
#define EPCTRL_EP_TYPE_ISO 1
#define EPCTRL_EP_TYPE_BULK 2
#define EPCTRL_EP_TYPE_INTERRUPT 3
#define EPCTRL_TX_EP_TYPE_SHIFT 18
#define EPCTRL_RX_EP_TYPE_SHIFT 2
/* SNOOPn Register Bit Masks */
#define SNOOP_ADDRESS_MASK 0xFFFFF000
#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */
#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */
#define SNOOP_SIZE_8KB 0x0C
#define SNOOP_SIZE_16KB 0x0D
#define SNOOP_SIZE_32KB 0x0E
#define SNOOP_SIZE_64KB 0x0F
#define SNOOP_SIZE_128KB 0x10
#define SNOOP_SIZE_256KB 0x11
#define SNOOP_SIZE_512KB 0x12
#define SNOOP_SIZE_1MB 0x13
#define SNOOP_SIZE_2MB 0x14
#define SNOOP_SIZE_4MB 0x15
#define SNOOP_SIZE_8MB 0x16
#define SNOOP_SIZE_16MB 0x17
#define SNOOP_SIZE_32MB 0x18
#define SNOOP_SIZE_64MB 0x19
#define SNOOP_SIZE_128MB 0x1A
#define SNOOP_SIZE_256MB 0x1B
#define SNOOP_SIZE_512MB 0x1C
#define SNOOP_SIZE_1GB 0x1D
#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */
/* pri_ctrl Register Bit Masks */
#define PRI_CTRL_PRI_LVL1 0x0000000C
#define PRI_CTRL_PRI_LVL0 0x00000003
/* si_ctrl Register Bit Masks */
#define SI_CTRL_ERR_DISABLE 0x00000010
#define SI_CTRL_IDRC_DISABLE 0x00000008
#define SI_CTRL_RD_SAFE_EN 0x00000004
#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
/* control Register Bit Masks */
#define USB_CTRL_IOENB 0x00000004
#define USB_CTRL_ULPI_INT0EN 0x00000001
[2]
#define ABS_AHBBURST (0x0090UL)
#define ABS_AHBMODE (0x0098UL)
/* UDC register map */
#define ABS_CAPLENGTH (0x100UL)
#define ABS_HCCPARAMS (0x108UL)
#define ABS_DCCPARAMS (0x124UL)
#define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
/* offset to CAPLENTGH (addr + data) */
#define CAP_USBCMD (0x000UL)
#define CAP_USBSTS (0x004UL)
#define CAP_USBINTR (0x008UL)
#define CAP_DEVICEADDR (0x014UL)
#define CAP_ENDPTLISTADDR (0x018UL)
#define CAP_PORTSC (0x044UL)
#define CAP_DEVLC (0x084UL)
#define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
#define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
#define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
#define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
#define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
#define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
#define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
#define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
/* HCCPARAMS */
#define HCCPARAMS_LEN BIT(17)
/* DCCPARAMS */
#define DCCPARAMS_DEN (0x1F << 0)
#define DCCPARAMS_DC BIT(7)
/* TESTMODE */
#define TESTMODE_FORCE BIT(0)
/* USBCMD */
#define USBCMD_RS BIT(0)
#define USBCMD_RST BIT(1)
#define USBCMD_SUTW BIT(13)
/* USBSTS & USBINTR */
#define USBi_UI BIT(0)
#define USBi_UEI BIT(1)
#define USBi_PCI BIT(2)
#define USBi_URI BIT(6)
#define USBi_SLI BIT(8)
/* DEVICEADDR */
#define DEVICEADDR_USBADRA BIT(24)
#define DEVICEADDR_USBADR (0x7FUL << 25)
/* PORTSC */
#define PORTSC_SUSP BIT(7)
#define PORTSC_HSP BIT(9)
#define PORTSC_PTC (0x0FUL << 16)
/* DEVLC */
#define DEVLC_PSPD (0x03UL << 25)
#define DEVLC_PSPD_HS (0x02UL << 25)
/* USBMODE */
#define USBMODE_CM (0x03UL << 0)
#define USBMODE_CM_IDLE (0x00UL << 0)
#define USBMODE_CM_DEVICE (0x02UL << 0)
#define USBMODE_CM_HOST (0x03UL << 0)
#define USBMODE_SLOM BIT(3)
#define USBMODE_SDIS BIT(4)
/* ENDPTCTRL */
#define ENDPTCTRL_RXS BIT(0)
#define ENDPTCTRL_RXT (0x03UL << 2)
#define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
#define ENDPTCTRL_RXE BIT(7)
#define ENDPTCTRL_TXS BIT(16)
#define ENDPTCTRL_TXT (0x03UL << 18)
#define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
#define ENDPTCTRL_TXE BIT(23)
[3]
#define CAPLENGTH_MASK (0xff)
#define DCCPARAMS_DEN_MASK (0x1f)
#define HCSPARAMS_PPC (0x10)
/* Frame Index Register Bit Masks */
#define USB_FRINDEX_MASKS 0x3fff
/* Command Register Bit Masks */
#define USBCMD_RUN_STOP (0x00000001)
#define USBCMD_CTRL_RESET (0x00000002)
#define USBCMD_SETUP_TRIPWIRE_SET (0x00002000)
#define USBCMD_SETUP_TRIPWIRE_CLEAR (~USBCMD_SETUP_TRIPWIRE_SET)
#define USBCMD_ATDTW_TRIPWIRE_SET (0x00004000)
#define USBCMD_ATDTW_TRIPWIRE_CLEAR (~USBCMD_ATDTW_TRIPWIRE_SET)
/* bit 15,3,2 are for frame list size */
#define USBCMD_FRAME_SIZE_1024 (0x00000000) /* 000 */
#define USBCMD_FRAME_SIZE_512 (0x00000004) /* 001 */
#define USBCMD_FRAME_SIZE_256 (0x00000008) /* 010 */
#define USBCMD_FRAME_SIZE_128 (0x0000000C) /* 011 */
#define USBCMD_FRAME_SIZE_64 (0x00008000) /* 100 */
#define USBCMD_FRAME_SIZE_32 (0x00008004) /* 101 */
#define USBCMD_FRAME_SIZE_16 (0x00008008) /* 110 */
#define USBCMD_FRAME_SIZE_8 (0x0000800C) /* 111 */
#define EPCTRL_TX_ALL_MASK (0xFFFF0000)
#define EPCTRL_RX_ALL_MASK (0x0000FFFF)
#define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000)
#define EPCTRL_TX_EP_STALL (0x00010000)
#define EPCTRL_RX_EP_STALL (0x00000001)
#define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040)
#define EPCTRL_RX_ENABLE (0x00000080)
#define EPCTRL_TX_ENABLE (0x00800000)
#define EPCTRL_CONTROL (0x00000000)
#define EPCTRL_ISOCHRONOUS (0x00040000)
#define EPCTRL_BULK (0x00080000)
#define EPCTRL_INT (0x000C0000)
#define EPCTRL_TX_TYPE (0x000C0000)
#define EPCTRL_RX_TYPE (0x0000000C)
#define EPCTRL_DATA_TOGGLE_INHIBIT (0x00000020)
#define EPCTRL_TX_EP_TYPE_SHIFT (18)
#define EPCTRL_RX_EP_TYPE_SHIFT (2)
#define EPCOMPLETE_MAX_ENDPOINTS (16)
/* endpoint list address bit masks */
#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
#define PORTSCX_W1C_BITS 0x2a
#define PORTSCX_PORT_RESET 0x00000100
#define PORTSCX_PORT_POWER 0x00001000
#define PORTSCX_FORCE_FULL_SPEED_CONNECT 0x01000000
#define PORTSCX_PAR_XCVR_SELECT 0xC0000000
#define PORTSCX_PORT_FORCE_RESUME 0x00000040
#define PORTSCX_PORT_SUSPEND 0x00000080
#define PORTSCX_PORT_SPEED_FULL 0x00000000
#define PORTSCX_PORT_SPEED_LOW 0x04000000
#define PORTSCX_PORT_SPEED_HIGH 0x08000000
#define PORTSCX_PORT_SPEED_MASK 0x0C000000
/* USB MODE Register Bit Masks */
#define USBMODE_CTRL_MODE_IDLE 0x00000000
#define USBMODE_CTRL_MODE_DEVICE 0x00000002
#define USBMODE_CTRL_MODE_HOST 0x00000003
#define USBMODE_CTRL_MODE_RSV 0x00000001
#define USBMODE_SETUP_LOCK_OFF 0x00000008
#define USBMODE_STREAM_DISABLE 0x00000010
/* USB STS Register Bit Masks */
#define USBSTS_INT 0x00000001
#define USBSTS_ERR 0x00000002
#define USBSTS_PORT_CHANGE 0x00000004
#define USBSTS_FRM_LST_ROLL 0x00000008
#define USBSTS_SYS_ERR 0x00000010
#define USBSTS_IAA 0x00000020
#define USBSTS_RESET 0x00000040
#define USBSTS_SOF 0x00000080
#define USBSTS_SUSPEND 0x00000100
#define USBSTS_HC_HALTED 0x00001000
#define USBSTS_RCL 0x00002000
#define USBSTS_PERIODIC_SCHEDULE 0x00004000
#define USBSTS_ASYNC_SCHEDULE 0x00008000
/* Interrupt Enable Register Bit Masks */
#define USBINTR_INT_EN (0x00000001)
#define USBINTR_ERR_INT_EN (0x00000002)
#define USBINTR_PORT_CHANGE_DETECT_EN (0x00000004)
#define USBINTR_ASYNC_ADV_AAE (0x00000020)
#define USBINTR_ASYNC_ADV_AAE_ENABLE (0x00000020)
#define USBINTR_ASYNC_ADV_AAE_DISABLE (0xFFFFFFDF)
#define USBINTR_RESET_EN (0x00000040)
#define USBINTR_SOF_UFRAME_EN (0x00000080)
#define USBINTR_DEVICE_SUSPEND (0x00000100)
#define USB_DEVICE_ADDRESS_MASK (0xfe000000)
#define USB_DEVICE_ADDRESS_BIT_SHIFT (25)
struct mv_cap_regs {
u32 caplength_hciversion;
u32 hcsparams; /* HC structural parameters */
u32 hccparams; /* HC Capability Parameters*/
u32 reserved[5];
u32 dciversion; /* DC version number and reserved 16 bits */
u32 dccparams; /* DC Capability Parameters */
};
struct mv_op_regs {
u32 usbcmd; /* Command register */
u32 usbsts; /* Status register */
u32 usbintr; /* Interrupt enable */
u32 frindex; /* Frame index */
u32 reserved1[1];
u32 deviceaddr; /* Device Address */
u32 eplistaddr; /* Endpoint List Address */
u32 ttctrl; /* HOST TT status and control */
u32 burstsize; /* Programmable Burst Size */
u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
u32 reserved[4];
u32 epnak; /* Endpoint NAK */
u32 epnaken; /* Endpoint NAK Enable */
u32 configflag; /* Configured Flag register */
u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
u32 otgsc;
u32 usbmode; /* USB Host/Device mode */
u32 epsetupstat; /* Endpoint Setup Status */
u32 epprime; /* Endpoint Initialize */
u32 epflush; /* Endpoint De-initialize */
u32 epstatus; /* Endpoint Status */
u32 epcomplete; /* Endpoint Interrupt On Complete */
u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
u32 mcr; /* Mux Control */
u32 isr; /* Interrupt Status */
u32 ier; /* Interrupt Enable */
};
[4]
/* device memory space registers */
/* Capability Registers, BAR0 + CAP_REG_OFFSET */
struct langwell_cap_regs {
/* offset: 0x0 */
u8 caplength; /* offset of Operational Register */
u8 _reserved3;
u16 hciversion; /* H: BCD encoding of host version */
u32 hcsparams; /* H: host port steering logic capability */
u32 hccparams; /* H: host multiple mode control capability */
#define HCC_LEN BIT(17) /* Link power management (LPM) capability */
u8 _reserved4[0x20-0xc];
/* offset: 0x20 */
u16 dciversion; /* BCD encoding of device version */
u8 _reserved5[0x24-0x22];
u32 dccparams; /* overall device controller capability */
#define HOSTCAP BIT(8) /* host capable */
#define DEVCAP BIT(7) /* device capable */
#define DEN(d) \
(((d)>>0)&0x1f) /* bits 4:0, device endpoint number */
} __attribute__ ((packed));
/* Operational Registers, BAR0 + OP_REG_OFFSET */
struct langwell_op_regs {
/* offset: 0x28 */
u32 extsts;
#define EXTS_TI1 BIT(4) /* general purpose timer interrupt 1 */
#define EXTS_TI1TI0 BIT(3) /* general purpose timer interrupt 0 */
#define EXTS_TI1UPI BIT(2) /* USB host periodic interrupt */
#define EXTS_TI1UAI BIT(1) /* USB host asynchronous interrupt */
#define EXTS_TI1NAKI BIT(0) /* NAK interrupt */
u32 extintr;
#define EXTI_TIE1 BIT(4) /* general purpose timer interrupt enable 1 */
#define EXTI_TIE0 BIT(3) /* general purpose timer interrupt enable 0 */
#define EXTI_UPIE BIT(2) /* USB host periodic interrupt enable */
#define EXTI_UAIE BIT(1) /* USB host asynchronous interrupt enable */
#define EXTI_NAKE BIT(0) /* NAK interrupt enable */
/* offset: 0x30 */
u32 usbcmd;
#define CMD_HIRD(u) \
(((u)>>24)&0xf) /* bits 27:24, host init resume duration */
#define CMD_ITC(u) \
(((u)>>16)&0xff) /* bits 23:16, interrupt threshold control */
#define CMD_PPE BIT(15) /* per-port change events enable */
#define CMD_ATDTW BIT(14) /* add dTD tripwire */
#define CMD_SUTW BIT(13) /* setup tripwire */
#define CMD_ASPE BIT(11) /* asynchronous schedule park mode enable */
#define CMD_FS2 BIT(10) /* frame list size */
#define CMD_ASP1 BIT(9) /* asynchronous schedule park mode count */
#define CMD_ASP0 BIT(8)
#define CMD_LR BIT(7) /* light host/device controller reset */
#define CMD_IAA BIT(6) /* interrupt on async advance doorbell */
#define CMD_ASE BIT(5) /* asynchronous schedule enable */
#define CMD_PSE BIT(4) /* periodic schedule enable */
#define CMD_FS1 BIT(3)
#define CMD_FS0 BIT(2)
#define CMD_RST BIT(1) /* controller reset */
#define CMD_RUNSTOP BIT(0) /* run/stop */
u32 usbsts;
#define STS_PPCI(u) \
(((u)>>16)&0xffff) /* bits 31:16, port-n change detect */
#define STS_AS BIT(15) /* asynchronous schedule status */
#define STS_PS BIT(14) /* periodic schedule status */
#define STS_RCL BIT(13) /* reclamation */
#define STS_HCH BIT(12) /* HC halted */
#define STS_ULPII BIT(10) /* ULPI interrupt */
#define STS_SLI BIT(8) /* DC suspend */
#define STS_SRI BIT(7) /* SOF received */
#define STS_URI BIT(6) /* USB reset received */
#define STS_AAI BIT(5) /* interrupt on async advance */
#define STS_SEI BIT(4) /* system error */
#define STS_FRI BIT(3) /* frame list rollover */
#define STS_PCI BIT(2) /* port change detect */
#define STS_UEI BIT(1) /* USB error interrupt */
#define STS_UI BIT(0) /* USB interrupt */
u32 usbintr;
/* bits 31:16, per-port interrupt enable */
#define INTR_PPCE(u) (((u)>>16)&0xffff)
#define INTR_ULPIE BIT(10) /* ULPI enable */
#define INTR_SLE BIT(8) /* DC sleep/suspend enable */
#define INTR_SRE BIT(7) /* SOF received enable */
#define INTR_URE BIT(6) /* USB reset enable */
#define INTR_AAE BIT(5) /* interrupt on async advance enable */
#define INTR_SEE BIT(4) /* system error enable */
#define INTR_FRE BIT(3) /* frame list rollover enable */
#define INTR_PCE BIT(2) /* port change detect enable */
#define INTR_UEE BIT(1) /* USB error interrupt enable */
#define INTR_UE BIT(0) /* USB interrupt enable */
u32 frindex; /* frame index */
#define FRINDEX_MASK (0x3fff << 0)
u32 ctrldssegment; /* not used */
u32 deviceaddr;
#define USBADR_SHIFT 25
#define USBADR(d) \
(((d)>>25)&0x7f) /* bits 31:25, device address */
#define USBADR_MASK (0x7f << 25)
#define USBADRA BIT(24) /* device address advance */
u32 endpointlistaddr;/* endpoint list top memory address */
/* bits 31:11, endpoint list pointer */
#define EPBASE(d) (((d)>>11)&0x1fffff)
#define ENDPOINTLISTADDR_MASK (0x1fffff << 11)
u32 ttctrl; /* H: TT operatin, not used */
/* offset: 0x50 */
u32 burstsize; /* burst size of data movement */
#define TXPBURST(b) \
(((b)>>8)&0xff) /* bits 15:8, TX burst length */
#define RXPBURST(b) \
(((b)>>0)&0xff) /* bits 7:0, RX burst length */
u32 txfilltuning; /* TX tuning */
u32 txttfilltuning; /* H: TX TT tuning */
u32 ic_usb; /* control the IC_USB FS/LS transceiver */
/* offset: 0x60 */
u32 ulpi_viewport; /* indirect access to ULPI PHY */
#define ULPIWU BIT(31) /* ULPI wakeup */
#define ULPIRUN BIT(30) /* ULPI read/write run */
#define ULPIRW BIT(29) /* ULPI read/write control */
#define ULPISS BIT(27) /* ULPI sync state */
#define ULPIPORT(u) \
(((u)>>24)&7) /* bits 26:24, ULPI port number */
#define ULPIADDR(u) \
(((u)>>16)&0xff) /* bits 23:16, ULPI data address */
#define ULPIDATRD(u) \
(((u)>>8)&0xff) /* bits 15:8, ULPI data read */
#define ULPIDATWR(u) \
(((u)>>0)&0xff) /* bits 7:0, ULPI date write */
u8 _reserved6[0x70-0x64];
/* offset: 0x70 */
u32 configflag; /* H: not used */
u32 portsc1; /* port status */
#define DA(p) \
(((p)>>25)&0x7f) /* bits 31:25, device address */
#define PORTS_SSTS (BIT(24) | BIT(23)) /* suspend status */
#define PORTS_WKOC BIT(22) /* wake on over-current enable */
#define PORTS_WKDS BIT(21) /* wake on disconnect enable */
#define PORTS_WKCN BIT(20) /* wake on connect enable */
#define PORTS_PTC(p) (((p)>>16)&0xf) /* bits 19:16, port test control */
#define PORTS_PIC (BIT(15) | BIT(14)) /* port indicator control */
#define PORTS_PO BIT(13) /* port owner */
#define PORTS_PP BIT(12) /* port power */
#define PORTS_LS (BIT(11) | BIT(10)) /* line status */
#define PORTS_SLP BIT(9) /* suspend using L1 */
#define PORTS_PR BIT(8) /* port reset */
#define PORTS_SUSP BIT(7) /* suspend */
#define PORTS_FPR BIT(6) /* force port resume */
#define PORTS_OCC BIT(5) /* over-current change */
#define PORTS_OCA BIT(4) /* over-current active */
#define PORTS_PEC BIT(3) /* port enable/disable change */
#define PORTS_PE BIT(2) /* port enable/disable */
#define PORTS_CSC BIT(1) /* connect status change */
#define PORTS_CCS BIT(0) /* current connect status */
u8 _reserved7[0xb4-0x78];
/* offset: 0xb4 */
u32 devlc; /* control LPM and each USB port behavior */
/* bits 31:29, parallel transceiver select */
#define LPM_PTS(d) (((d)>>29)&7)
#define LPM_STS BIT(28) /* serial transceiver select */
#define LPM_PTW BIT(27) /* parallel transceiver width */
#define LPM_PSPD(d) (((d)>>25)&3) /* bits 26:25, port speed */
#define LPM_PSPD_MASK (BIT(26) | BIT(25))
#define LPM_SPEED_FULL 0
#define LPM_SPEED_LOW 1
#define LPM_SPEED_HIGH 2
#define LPM_SRT BIT(24) /* shorten reset time */
#define LPM_PFSC BIT(23) /* port force full speed connect */
#define LPM_PHCD BIT(22) /* PHY low power suspend clock disable */
#define LPM_STL BIT(16) /* STALL reply to LPM token */
#define LPM_BA(d) \
(((d)>>1)&0x7ff) /* bits 11:1, BmAttributes */
#define LPM_NYT_ACK BIT(0) /* NYET/ACK reply to LPM token */
u8 _reserved8[0xf4-0xb8];
/* offset: 0xf4 */
u32 otgsc; /* On-The-Go status and control */
#define OTGSC_DPIE BIT(30) /* data pulse interrupt enable */
#define OTGSC_MSE BIT(29) /* 1 ms timer interrupt enable */
#define OTGSC_BSEIE BIT(28) /* B session end interrupt enable */
#define OTGSC_BSVIE BIT(27) /* B session valid interrupt enable */
#define OTGSC_ASVIE BIT(26) /* A session valid interrupt enable */
#define OTGSC_AVVIE BIT(25) /* A VBUS valid interrupt enable */
#define OTGSC_IDIE BIT(24) /* USB ID interrupt enable */
#define OTGSC_DPIS BIT(22) /* data pulse interrupt status */
#define OTGSC_MSS BIT(21) /* 1 ms timer interrupt status */
#define OTGSC_BSEIS BIT(20) /* B session end interrupt status */
#define OTGSC_BSVIS BIT(19) /* B session valid interrupt status */
#define OTGSC_ASVIS BIT(18) /* A session valid interrupt status */
#define OTGSC_AVVIS BIT(17) /* A VBUS valid interrupt status */
#define OTGSC_IDIS BIT(16) /* USB ID interrupt status */
#define OTGSC_DPS BIT(14) /* data bus pulsing status */
#define OTGSC_MST BIT(13) /* 1 ms timer toggle */
#define OTGSC_BSE BIT(12) /* B session end */
#define OTGSC_BSV BIT(11) /* B session valid */
#define OTGSC_ASV BIT(10) /* A session valid */
#define OTGSC_AVV BIT(9) /* A VBUS valid */
#define OTGSC_USBID BIT(8) /* USB ID */
#define OTGSC_HABA BIT(7) /* hw assist B-disconnect to A-connect */
#define OTGSC_HADP BIT(6) /* hw assist data pulse */
#define OTGSC_IDPU BIT(5) /* ID pullup */
#define OTGSC_DP BIT(4) /* data pulsing */
#define OTGSC_OT BIT(3) /* OTG termination */
#define OTGSC_HAAR BIT(2) /* hw assist auto reset */
#define OTGSC_VC BIT(1) /* VBUS charge */
#define OTGSC_VD BIT(0) /* VBUS discharge */
u32 usbmode;
#define MODE_VBPS BIT(5) /* R/W VBUS power select */
#define MODE_SDIS BIT(4) /* R/W stream disable mode */
#define MODE_SLOM BIT(3) /* R/W setup lockout mode */
#define MODE_ENSE BIT(2) /* endian select */
#define MODE_CM(u) (((u)>>0)&3) /* bits 1:0, controller mode */
#define MODE_IDLE 0
#define MODE_DEVICE 2
#define MODE_HOST 3
u8 _reserved9[0x100-0xfc];
/* offset: 0x100 */
u32 endptnak;
#define EPTN(e) \
(((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK */
#define EPRN(e) \
(((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK */
u32 endptnaken;
#define EPTNE(e) \
(((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK enable */
#define EPRNE(e) \
(((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK enable */
u32 endptsetupstat;
#define SETUPSTAT_MASK (0xffff << 0) /* bits 15:0 */
#define EP0SETUPSTAT_MASK 1
u32 endptprime;
/* bits 31:16, prime endpoint transmit buffer */
#define PETB(e) (((e)>>16)&0xffff)
/* bits 15:0, prime endpoint receive buffer */
#define PERB(e) (((e)>>0)&0xffff)
/* offset: 0x110 */
u32 endptflush;
/* bits 31:16, flush endpoint transmit buffer */
#define FETB(e) (((e)>>16)&0xffff)
/* bits 15:0, flush endpoint receive buffer */
#define FERB(e) (((e)>>0)&0xffff)
u32 endptstat;
/* bits 31:16, endpoint transmit buffer ready */
#define ETBR(e) (((e)>>16)&0xffff)
/* bits 15:0, endpoint receive buffer ready */
#define ERBR(e) (((e)>>0)&0xffff)
u32 endptcomplete;
/* bits 31:16, endpoint transmit complete event */
#define ETCE(e) (((e)>>16)&0xffff)
/* bits 15:0, endpoint receive complete event */
#define ERCE(e) (((e)>>0)&0xffff)
/* offset: 0x11c */
u32 endptctrl[16];
#define EPCTRL_TXE BIT(23) /* TX endpoint enable */
#define EPCTRL_TXR BIT(22) /* TX data toggle reset */
#define EPCTRL_TXI BIT(21) /* TX data toggle inhibit */
#define EPCTRL_TXT(e) (((e)>>18)&3) /* bits 19:18, TX endpoint type */
#define EPCTRL_TXT_SHIFT 18
#define EPCTRL_TXD BIT(17) /* TX endpoint data source */
#define EPCTRL_TXS BIT(16) /* TX endpoint STALL */
#define EPCTRL_RXE BIT(7) /* RX endpoint enable */
#define EPCTRL_RXR BIT(6) /* RX data toggle reset */
#define EPCTRL_RXI BIT(5) /* RX data toggle inhibit */
#define EPCTRL_RXT(e) (((e)>>2)&3) /* bits 3:2, RX endpoint type */
#define EPCTRL_RXT_SHIFT 2 /* bits 19:18, TX endpoint type */
#define EPCTRL_RXD BIT(1) /* RX endpoint data sink */
#define EPCTRL_RXS BIT(0) /* RX endpoint STALL */
} __attribute__ ((packed));
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