Hello,
Benoit Goby a écrit :
Interface used by Tegra's gadget driver and ehci driver
to power on and configure the USB PHYs.
+ */
+
+#include <linux/resource.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <mach/usb_phy.h>
+#include <mach/iomap.h>
+
+#define USB_USBSTS 0x144
+#define USB_USBSTS_PCI (1 << 2)
+
+#define ULPI_VIEWPORT 0x170
It look like your core is a arc/chipidea/mips one that is already used
on other product (msm) for example.
Can't you merge with them ?
for example
> +static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
> +{
> + unsigned long timeout = 2000;
> + do {
> + if ((readl(reg) & mask) == result)
> + return 0;
> + udelay(1);
> + timeout--;
> + } while (timeout);
> + return -1;
> +}
> +static void ulpi_viewport_write(struct tegra_usb_phy *phy, u8 addr,
u8 data)
> +{
> + unsigned long val;
> + void __iomem *base = phy->regs;
> +
> + val = ULPI_RUN | ULPI_RD_RW_WRITE | ULPI_PORT(0);
> + val |= ULPI_ADDR(addr) | ULPI_DATA_WR(data);
> + writel(val, base + ULPI_VIEWPORT);
> +
> + if (utmi_wait_register(base + ULPI_VIEWPORT, ULPI_RUN, 0))
> + pr_err("%s: timeout accessing ulpi phy\n", __func__);
> +}
look very similar to what is in drivers/usb/otg/msm72k_otg.c
+static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+ struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
+ int cnt = 0;
+
+ /* initiate write operation */
+ writel(ULPI_RUN | ULPI_WRITE |
+ ULPI_ADDR(reg) | ULPI_DATA(val),
+ USB_ULPI_VIEWPORT);
+
+ /* wait for completion */
+ while (cnt < ULPI_IO_TIMEOUT_USEC) {
+ if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= ULPI_IO_TIMEOUT_USEC) {
+ dev_err(otg->dev, "ulpi_write: timeout\n");
+ return -ETIMEDOUT;
+ }
+ return 0;
+}
Matthieu
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