Hi Sarah, I've got a Buffalo USB3.0 external hub(BSH4A03U3). It does not work on my platform with 3.0 mode. The hub contains a USB3.0 hub and a USB2.0 hub. When usbcore issue a get_hub_descriptor command to the 3.0 hub, xHC returns an event with Stall Error and get_hub_descriptor() fails. The USB2.0 hub works OK. Dmesg attached. Do you know this issue? Is it a device issue or driver issue? Thanks, Andiry
[ 82.686463] xhci_hcd 0000:00:10.0: op reg status = 00000018 [ 82.686467] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 82.686470] xhci_hcd 0000:00:10.0: @5d22c400 01000000 00000000 01000000 00008801 [ 82.686473] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h18, 4'hf); [ 82.686475] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.686477] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 82.686479] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_port_status [ 82.686481] xhci_hcd 0000:00:10.0: Port Status Change Event for port 1 [ 82.686486] xhci_hcd 0000:00:10.0: resume root hub [ 82.686494] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c410 (DMA) [ 82.686507] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_port_status [ 82.686509] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.686516] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c418, 4'hf); [ 82.686527] usb usb6: usb wakeup-resume [ 82.686531] usb usb6: usb auto-resume [ 82.686533] xhci_hcd 0000:00:10.0: resume root hub [ 82.686537] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918020, 32'h1, 4'hf); [ 82.686543] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918450, 32'h2a0, 4'hf); [ 82.686549] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918440, 32'h2a0, 4'hf); [ 82.686555] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918430, 32'h2a0, 4'hf); [ 82.686562] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918420, 32'h1201, 4'hf); [ 82.686569] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918020, 32'h5, 4'hf); [ 82.687988] xhci_hcd 0000:00:10.0: op reg status = 00000018 [ 82.687991] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 82.687994] xhci_hcd 0000:00:10.0: @5d22c410 03000000 00000000 01000000 00008801 [ 82.687996] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h18, 4'hf); [ 82.687999] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.688000] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 82.688002] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_port_status [ 82.688004] xhci_hcd 0000:00:10.0: Port Status Change Event for port 3 [ 82.688008] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c420 (DMA) [ 82.688015] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_port_status [ 82.688017] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.688021] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c428, 4'hf); [ 82.700125] hub 6-0:1.0: hub_resume [ 82.700136] xhci_hcd 0000:00:10.0: get port status, actual port 0 status = 0x21203 [ 82.700139] xhci_hcd 0000:00:10.0: Get port status returned 0x18103 [ 82.700144] hub 6-0:1.0: port 1: status 8103 change 0001 [ 82.700149] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918420, 32'h21201, 4'hf); [ 82.700153] xhci_hcd 0000:00:10.0: clear port connect change, actual port 0 status = 0x1203 [ 82.700158] xhci_hcd 0000:00:10.0: get port status, actual port 1 status = 0x2a0 [ 82.700160] xhci_hcd 0000:00:10.0: Get port status returned 0x100 [ 82.700164] xhci_hcd 0000:00:10.0: get port status, actual port 2 status = 0x202e1 [ 82.700166] xhci_hcd 0000:00:10.0: Get port status returned 0x10101 [ 82.700169] hub 6-0:1.0: port 3: status 0101 change 0001 [ 82.700172] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918440, 32'h202e1, 4'hf); [ 82.700176] xhci_hcd 0000:00:10.0: clear port connect change, actual port 2 status = 0x2e1 [ 82.700181] xhci_hcd 0000:00:10.0: get port status, actual port 3 status = 0x2a0 [ 82.700183] xhci_hcd 0000:00:10.0: Get port status returned 0x100 [ 82.810111] hub 6-0:1.0: state 7 ports 4 chg 000a evt 0000 [ 82.810125] xhci_hcd 0000:00:10.0: get port status, actual port 0 status = 0x1203 [ 82.810127] xhci_hcd 0000:00:10.0: Get port status returned 0x8103 [ 82.810133] hub 6-0:1.0: port 1, status 8103, change 0000, 5.0 Gb/s [ 82.810138] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 82.810140] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c010 (DMA) [ 82.810142] xhci_hcd 0000:00:10.0: // Ding dong! [ 82.810146] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 82.810201] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 82.810205] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 82.810209] xhci_hcd 0000:00:10.0: @5d22c420 5d22c000 00000000 01000000 01008401 [ 82.810211] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 82.810214] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.810216] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 82.810218] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 82.810226] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c010 (DMA) [ 82.810228] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 82.810230] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c430 (DMA) [ 82.810232] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.810236] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c438, 4'hf); [ 82.810254] xhci_hcd 0000:00:10.0: Slot 1 output ctx = 0x5a0cf000 (dma) [ 82.810258] xhci_hcd 0000:00:10.0: Slot 1 input ctx = 0x5a0d0000 (dma) [ 82.810261] xhci_hcd 0000:00:10.0: Allocating ring at ffff88005a65a060 [ 82.810264] xhci_hcd 0000:00:10.0: Allocating priv segment structure at ffff88005badcea0 [ 82.810267] xhci_hcd 0000:00:10.0: // Allocating segment at ffff88005d22c800 (virtual) 0x5d22c800 (DMA) [ 82.810271] xhci_hcd 0000:00:10.0: Linking segment 0x5d22c800 to segment 0x5d22c800 (DMA) [ 82.810274] xhci_hcd 0000:00:10.0: Wrote link toggle flag to segment ffff88005badcea0 (virtual), 0x5d22c800 (DMA) [ 82.810277] xhci_hcd 0000:00:10.0: Set slot id 1 dcbaa entry ffff88005d984008 to 0x5a0cf000 [ 82.810286] xhci_hcd 0000:00:10.0: Set root hub portnum to 1 [ 82.810289] xhci_hcd 0000:00:10.0: udev->tt = (null) [ 82.810291] xhci_hcd 0000:00:10.0: udev->ttport = 0x0 [ 82.810293] xhci_hcd 0000:00:10.0: Slot ID 1 Input Context: [ 82.810296] xhci_hcd 0000:00:10.0: @ffff88005a0d0000 (virt) @5a0d0000 (dma) 0x000000 - drop flags [ 82.810299] xhci_hcd 0000:00:10.0: @ffff88005a0d0004 (virt) @5a0d0004 (dma) 0x000003 - add flags [ 82.810302] xhci_hcd 0000:00:10.0: @ffff88005a0d0008 (virt) @5a0d0008 (dma) 0x000000 - rsvd2[0] [ 82.810305] xhci_hcd 0000:00:10.0: @ffff88005a0d000c (virt) @5a0d000c (dma) 0x000000 - rsvd2[1] [ 82.810308] xhci_hcd 0000:00:10.0: @ffff88005a0d0010 (virt) @5a0d0010 (dma) 0x000000 - rsvd2[2] [ 82.810310] xhci_hcd 0000:00:10.0: @ffff88005a0d0014 (virt) @5a0d0014 (dma) 0x000000 - rsvd2[3] [ 82.810313] xhci_hcd 0000:00:10.0: @ffff88005a0d0018 (virt) @5a0d0018 (dma) 0x000000 - rsvd2[4] [ 82.810316] xhci_hcd 0000:00:10.0: @ffff88005a0d001c (virt) @5a0d001c (dma) 0x000000 - rsvd2[5] [ 82.810318] xhci_hcd 0000:00:10.0: Slot Context: [ 82.810320] xhci_hcd 0000:00:10.0: @ffff88005a0d0020 (virt) @5a0d0020 (dma) 0x8400000 - dev_info [ 82.810323] xhci_hcd 0000:00:10.0: @ffff88005a0d0024 (virt) @5a0d0024 (dma) 0x010000 - dev_info2 [ 82.810326] xhci_hcd 0000:00:10.0: @ffff88005a0d0028 (virt) @5a0d0028 (dma) 0x000000 - tt_info [ 82.810329] xhci_hcd 0000:00:10.0: @ffff88005a0d002c (virt) @5a0d002c (dma) 0x000000 - dev_state [ 82.810331] xhci_hcd 0000:00:10.0: @ffff88005a0d0030 (virt) @5a0d0030 (dma) 0x000000 - rsvd[0] [ 82.810334] xhci_hcd 0000:00:10.0: @ffff88005a0d0034 (virt) @5a0d0034 (dma) 0x000000 - rsvd[1] [ 82.810337] xhci_hcd 0000:00:10.0: @ffff88005a0d0038 (virt) @5a0d0038 (dma) 0x000000 - rsvd[2] [ 82.810340] xhci_hcd 0000:00:10.0: @ffff88005a0d003c (virt) @5a0d003c (dma) 0x000000 - rsvd[3] [ 82.810342] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 82.810344] xhci_hcd 0000:00:10.0: @ffff88005a0d0040 (virt) @5a0d0040 (dma) 0x000000 - ep_info [ 82.810347] xhci_hcd 0000:00:10.0: @ffff88005a0d0044 (virt) @5a0d0044 (dma) 0x2000026 - ep_info2 [ 82.810350] xhci_hcd 0000:00:10.0: @ffff88005a0d0048 (virt) @5a0d0048 (dma) 0x5d22c801 - deq [ 82.810352] xhci_hcd 0000:00:10.0: @ffff88005a0d0050 (virt) @5a0d0050 (dma) 0x000000 - tx_info [ 82.810355] xhci_hcd 0000:00:10.0: @ffff88005a0d0054 (virt) @5a0d0054 (dma) 0x000000 - rsvd[0] [ 82.810358] xhci_hcd 0000:00:10.0: @ffff88005a0d0058 (virt) @5a0d0058 (dma) 0x000000 - rsvd[1] [ 82.810361] xhci_hcd 0000:00:10.0: @ffff88005a0d005c (virt) @5a0d005c (dma) 0x000000 - rsvd[2] [ 82.810363] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 82.810365] xhci_hcd 0000:00:10.0: @ffff88005a0d0060 (virt) @5a0d0060 (dma) 0x000000 - ep_info [ 82.810368] xhci_hcd 0000:00:10.0: @ffff88005a0d0064 (virt) @5a0d0064 (dma) 0x000000 - ep_info2 [ 82.810370] xhci_hcd 0000:00:10.0: @ffff88005a0d0068 (virt) @5a0d0068 (dma) 0x000000 - deq [ 82.810373] xhci_hcd 0000:00:10.0: @ffff88005a0d0070 (virt) @5a0d0070 (dma) 0x000000 - tx_info [ 82.810376] xhci_hcd 0000:00:10.0: @ffff88005a0d0074 (virt) @5a0d0074 (dma) 0x000000 - rsvd[0] [ 82.810379] xhci_hcd 0000:00:10.0: @ffff88005a0d0078 (virt) @5a0d0078 (dma) 0x000000 - rsvd[1] [ 82.810381] xhci_hcd 0000:00:10.0: @ffff88005a0d007c (virt) @5a0d007c (dma) 0x000000 - rsvd[2] [ 82.810384] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 82.810386] xhci_hcd 0000:00:10.0: @ffff88005a0d0080 (virt) @5a0d0080 (dma) 0x000000 - ep_info [ 82.810389] xhci_hcd 0000:00:10.0: @ffff88005a0d0084 (virt) @5a0d0084 (dma) 0x000000 - ep_info2 [ 82.810391] xhci_hcd 0000:00:10.0: @ffff88005a0d0088 (virt) @5a0d0088 (dma) 0x000000 - deq [ 82.810394] xhci_hcd 0000:00:10.0: @ffff88005a0d0090 (virt) @5a0d0090 (dma) 0x000000 - tx_info [ 82.810396] xhci_hcd 0000:00:10.0: @ffff88005a0d0094 (virt) @5a0d0094 (dma) 0x000000 - rsvd[0] [ 82.810399] xhci_hcd 0000:00:10.0: @ffff88005a0d0098 (virt) @5a0d0098 (dma) 0x000000 - rsvd[1] [ 82.810402] xhci_hcd 0000:00:10.0: @ffff88005a0d009c (virt) @5a0d009c (dma) 0x000000 - rsvd[2] [ 82.810405] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 82.810408] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c020 (DMA) [ 82.810409] xhci_hcd 0000:00:10.0: // Ding dong! [ 82.810448] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 82.812776] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 82.812780] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 82.812782] xhci_hcd 0000:00:10.0: @5d22c430 5d22c010 00000000 01000000 01008401 [ 82.812785] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 82.812787] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.812789] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 82.812791] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 82.812798] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c020 (DMA) [ 82.812800] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 82.812802] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c440 (DMA) [ 82.812804] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.812809] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c448, 4'hf); [ 82.812819] xhci_hcd 0000:00:10.0: Successful Address Device command [ 82.812823] xhci_hcd 0000:00:10.0: Op regs DCBAA ptr = 0x0000005d984000 [ 82.812826] xhci_hcd 0000:00:10.0: Slot ID 1 dcbaa entry @ffff88005d984008 = 0x0000005a0cf000 [ 82.812828] xhci_hcd 0000:00:10.0: Output Context DMA address = 0x5a0cf000 [ 82.812830] xhci_hcd 0000:00:10.0: Slot ID 1 Input Context: [ 82.812833] xhci_hcd 0000:00:10.0: @ffff88005a0d0000 (virt) @5a0d0000 (dma) 0x000000 - drop flags [ 82.812835] xhci_hcd 0000:00:10.0: @ffff88005a0d0004 (virt) @5a0d0004 (dma) 0x000003 - add flags [ 82.812838] xhci_hcd 0000:00:10.0: @ffff88005a0d0008 (virt) @5a0d0008 (dma) 0x000000 - rsvd2[0] [ 82.812841] xhci_hcd 0000:00:10.0: @ffff88005a0d000c (virt) @5a0d000c (dma) 0x000000 - rsvd2[1] [ 82.812843] xhci_hcd 0000:00:10.0: @ffff88005a0d0010 (virt) @5a0d0010 (dma) 0x000000 - rsvd2[2] [ 82.812845] xhci_hcd 0000:00:10.0: @ffff88005a0d0014 (virt) @5a0d0014 (dma) 0x000000 - rsvd2[3] [ 82.812848] xhci_hcd 0000:00:10.0: @ffff88005a0d0018 (virt) @5a0d0018 (dma) 0x000000 - rsvd2[4] [ 82.812850] xhci_hcd 0000:00:10.0: @ffff88005a0d001c (virt) @5a0d001c (dma) 0x000000 - rsvd2[5] [ 82.812853] xhci_hcd 0000:00:10.0: Slot Context: [ 82.812855] xhci_hcd 0000:00:10.0: @ffff88005a0d0020 (virt) @5a0d0020 (dma) 0x8400000 - dev_info [ 82.812857] xhci_hcd 0000:00:10.0: @ffff88005a0d0024 (virt) @5a0d0024 (dma) 0x010000 - dev_info2 [ 82.812860] xhci_hcd 0000:00:10.0: @ffff88005a0d0028 (virt) @5a0d0028 (dma) 0x000000 - tt_info [ 82.812862] xhci_hcd 0000:00:10.0: @ffff88005a0d002c (virt) @5a0d002c (dma) 0x000000 - dev_state [ 82.812865] xhci_hcd 0000:00:10.0: @ffff88005a0d0030 (virt) @5a0d0030 (dma) 0x000000 - rsvd[0] [ 82.812867] xhci_hcd 0000:00:10.0: @ffff88005a0d0034 (virt) @5a0d0034 (dma) 0x000000 - rsvd[1] [ 82.812869] xhci_hcd 0000:00:10.0: @ffff88005a0d0038 (virt) @5a0d0038 (dma) 0x000000 - rsvd[2] [ 82.812872] xhci_hcd 0000:00:10.0: @ffff88005a0d003c (virt) @5a0d003c (dma) 0x000000 - rsvd[3] [ 82.812874] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 82.812876] xhci_hcd 0000:00:10.0: @ffff88005a0d0040 (virt) @5a0d0040 (dma) 0x000000 - ep_info [ 82.812879] xhci_hcd 0000:00:10.0: @ffff88005a0d0044 (virt) @5a0d0044 (dma) 0x2000026 - ep_info2 [ 82.812881] xhci_hcd 0000:00:10.0: @ffff88005a0d0048 (virt) @5a0d0048 (dma) 0x5d22c801 - deq [ 82.812884] xhci_hcd 0000:00:10.0: @ffff88005a0d0050 (virt) @5a0d0050 (dma) 0x000000 - tx_info [ 82.812886] xhci_hcd 0000:00:10.0: @ffff88005a0d0054 (virt) @5a0d0054 (dma) 0x000000 - rsvd[0] [ 82.812889] xhci_hcd 0000:00:10.0: @ffff88005a0d0058 (virt) @5a0d0058 (dma) 0x000000 - rsvd[1] [ 82.812891] xhci_hcd 0000:00:10.0: @ffff88005a0d005c (virt) @5a0d005c (dma) 0x000000 - rsvd[2] [ 82.812893] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 82.812895] xhci_hcd 0000:00:10.0: @ffff88005a0d0060 (virt) @5a0d0060 (dma) 0x000000 - ep_info [ 82.812897] xhci_hcd 0000:00:10.0: @ffff88005a0d0064 (virt) @5a0d0064 (dma) 0x000000 - ep_info2 [ 82.812900] xhci_hcd 0000:00:10.0: @ffff88005a0d0068 (virt) @5a0d0068 (dma) 0x000000 - deq [ 82.812902] xhci_hcd 0000:00:10.0: @ffff88005a0d0070 (virt) @5a0d0070 (dma) 0x000000 - tx_info [ 82.812905] xhci_hcd 0000:00:10.0: @ffff88005a0d0074 (virt) @5a0d0074 (dma) 0x000000 - rsvd[0] [ 82.812907] xhci_hcd 0000:00:10.0: @ffff88005a0d0078 (virt) @5a0d0078 (dma) 0x000000 - rsvd[1] [ 82.812910] xhci_hcd 0000:00:10.0: @ffff88005a0d007c (virt) @5a0d007c (dma) 0x000000 - rsvd[2] [ 82.812912] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 82.812914] xhci_hcd 0000:00:10.0: @ffff88005a0d0080 (virt) @5a0d0080 (dma) 0x000000 - ep_info [ 82.812916] xhci_hcd 0000:00:10.0: @ffff88005a0d0084 (virt) @5a0d0084 (dma) 0x000000 - ep_info2 [ 82.812919] xhci_hcd 0000:00:10.0: @ffff88005a0d0088 (virt) @5a0d0088 (dma) 0x000000 - deq [ 82.812921] xhci_hcd 0000:00:10.0: @ffff88005a0d0090 (virt) @5a0d0090 (dma) 0x000000 - tx_info [ 82.812923] xhci_hcd 0000:00:10.0: @ffff88005a0d0094 (virt) @5a0d0094 (dma) 0x000000 - rsvd[0] [ 82.812926] xhci_hcd 0000:00:10.0: @ffff88005a0d0098 (virt) @5a0d0098 (dma) 0x000000 - rsvd[1] [ 82.812928] xhci_hcd 0000:00:10.0: @ffff88005a0d009c (virt) @5a0d009c (dma) 0x000000 - rsvd[2] [ 82.812930] xhci_hcd 0000:00:10.0: Slot ID 1 Output Context: [ 82.812932] xhci_hcd 0000:00:10.0: Slot Context: [ 82.812934] xhci_hcd 0000:00:10.0: @ffff88005a0cf000 (virt) @5a0cf000 (dma) 0x8400000 - dev_info [ 82.812937] xhci_hcd 0000:00:10.0: @ffff88005a0cf004 (virt) @5a0cf004 (dma) 0x010000 - dev_info2 [ 82.812940] xhci_hcd 0000:00:10.0: @ffff88005a0cf008 (virt) @5a0cf008 (dma) 0x000000 - tt_info [ 82.812942] xhci_hcd 0000:00:10.0: @ffff88005a0cf00c (virt) @5a0cf00c (dma) 0x10000001 - dev_state [ 82.812945] xhci_hcd 0000:00:10.0: @ffff88005a0cf010 (virt) @5a0cf010 (dma) 0x000000 - rsvd[0] [ 82.812948] xhci_hcd 0000:00:10.0: @ffff88005a0cf014 (virt) @5a0cf014 (dma) 0x000000 - rsvd[1] [ 82.812951] xhci_hcd 0000:00:10.0: @ffff88005a0cf018 (virt) @5a0cf018 (dma) 0x000000 - rsvd[2] [ 82.812953] xhci_hcd 0000:00:10.0: @ffff88005a0cf01c (virt) @5a0cf01c (dma) 0x000000 - rsvd[3] [ 82.812956] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 82.812958] xhci_hcd 0000:00:10.0: @ffff88005a0cf020 (virt) @5a0cf020 (dma) 0x000001 - ep_info [ 82.812961] xhci_hcd 0000:00:10.0: @ffff88005a0cf024 (virt) @5a0cf024 (dma) 0x2000026 - ep_info2 [ 82.812963] xhci_hcd 0000:00:10.0: @ffff88005a0cf028 (virt) @5a0cf028 (dma) 0x5d22c801 - deq [ 82.812966] xhci_hcd 0000:00:10.0: @ffff88005a0cf030 (virt) @5a0cf030 (dma) 0x000000 - tx_info [ 82.812969] xhci_hcd 0000:00:10.0: @ffff88005a0cf034 (virt) @5a0cf034 (dma) 0x000000 - rsvd[0] [ 82.812972] xhci_hcd 0000:00:10.0: @ffff88005a0cf038 (virt) @5a0cf038 (dma) 0x000000 - rsvd[1] [ 82.812974] xhci_hcd 0000:00:10.0: @ffff88005a0cf03c (virt) @5a0cf03c (dma) 0x000000 - rsvd[2] [ 82.812977] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 82.812979] xhci_hcd 0000:00:10.0: @ffff88005a0cf040 (virt) @5a0cf040 (dma) 0x000000 - ep_info [ 82.812982] xhci_hcd 0000:00:10.0: @ffff88005a0cf044 (virt) @5a0cf044 (dma) 0x000000 - ep_info2 [ 82.812984] xhci_hcd 0000:00:10.0: @ffff88005a0cf048 (virt) @5a0cf048 (dma) 0x000000 - deq [ 82.812987] xhci_hcd 0000:00:10.0: @ffff88005a0cf050 (virt) @5a0cf050 (dma) 0x000000 - tx_info [ 82.812990] xhci_hcd 0000:00:10.0: @ffff88005a0cf054 (virt) @5a0cf054 (dma) 0x000000 - rsvd[0] [ 82.812992] xhci_hcd 0000:00:10.0: @ffff88005a0cf058 (virt) @5a0cf058 (dma) 0x000000 - rsvd[1] [ 82.812995] xhci_hcd 0000:00:10.0: @ffff88005a0cf05c (virt) @5a0cf05c (dma) 0x000000 - rsvd[2] [ 82.812998] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 82.813000] xhci_hcd 0000:00:10.0: @ffff88005a0cf060 (virt) @5a0cf060 (dma) 0x000000 - ep_info [ 82.813002] xhci_hcd 0000:00:10.0: @ffff88005a0cf064 (virt) @5a0cf064 (dma) 0x000000 - ep_info2 [ 82.813005] xhci_hcd 0000:00:10.0: @ffff88005a0cf068 (virt) @5a0cf068 (dma) 0x000000 - deq [ 82.813008] xhci_hcd 0000:00:10.0: @ffff88005a0cf070 (virt) @5a0cf070 (dma) 0x000000 - tx_info [ 82.813010] xhci_hcd 0000:00:10.0: @ffff88005a0cf074 (virt) @5a0cf074 (dma) 0x000000 - rsvd[0] [ 82.813013] xhci_hcd 0000:00:10.0: @ffff88005a0cf078 (virt) @5a0cf078 (dma) 0x000000 - rsvd[1] [ 82.813016] xhci_hcd 0000:00:10.0: @ffff88005a0cf07c (virt) @5a0cf07c (dma) 0x000000 - rsvd[2] [ 82.813018] xhci_hcd 0000:00:10.0: Internal device address = 2 [ 82.813023] usb 6-1: new SuperSpeed USB device using xhci_hcd and address 2 [ 82.830144] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 82.830149] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 82.830152] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c810 (DMA) [ 82.830155] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c820 (DMA) [ 82.830157] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c830 (DMA) [ 82.830160] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 82.915782] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 82.915786] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 82.915789] xhci_hcd 0000:00:10.0: @5d22c440 5d22c820 00000000 01000000 01018001 [ 82.915791] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 82.915794] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.915796] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 82.915797] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 82.915799] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 82.915803] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560544 [ 82.915805] xhci_hcd 0000:00:10.0: Successful control transfer! [ 82.915808] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c810 (DMA) [ 82.915809] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c820 (DMA) [ 82.915811] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c830 (DMA) [ 82.915813] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c450 (DMA) [ 82.915816] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a0226c0, len = 8, status = 0 [ 82.915825] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 82.915827] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.915831] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c458, 4'hf); [ 82.915849] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 82.915851] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 82.915854] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c840 (DMA) [ 82.915856] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c850 (DMA) [ 82.915857] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c860 (DMA) [ 82.915861] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 82.970141] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 82.970145] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 82.970148] xhci_hcd 0000:00:10.0: @5d22c450 5d22c850 00000000 01000000 01018001 [ 82.970151] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 82.970153] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.970155] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 82.970157] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 82.970159] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 82.970163] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560592 [ 82.970165] xhci_hcd 0000:00:10.0: Successful control transfer! [ 82.970167] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c840 (DMA) [ 82.970169] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c850 (DMA) [ 82.970171] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c860 (DMA) [ 82.970173] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c460 (DMA) [ 82.970176] xhci_hcd 0000:00:10.0: Giveback URB ffff88005bbea840, len = 18, status = 0 [ 82.970185] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 82.970186] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 82.970191] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c468, 4'hf); [ 82.970212] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 82.970214] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 82.970216] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c870 (DMA) [ 82.970218] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c880 (DMA) [ 82.970220] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c890 (DMA) [ 82.970223] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.024401] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.024405] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.024408] xhci_hcd 0000:00:10.0: @5d22c460 5d22c880 00000000 01000000 01018001 [ 83.024411] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.024413] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.024415] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.024417] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.024419] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.024423] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560640 [ 83.024425] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.024427] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c870 (DMA) [ 83.024429] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c880 (DMA) [ 83.024431] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c890 (DMA) [ 83.024433] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c470 (DMA) [ 83.024436] xhci_hcd 0000:00:10.0: Giveback URB ffff88005bb49c00, len = 9, status = 0 [ 83.024445] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.024447] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.024451] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c478, 4'hf); [ 83.024467] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.024469] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.024472] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c8a0 (DMA) [ 83.024474] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c8b0 (DMA) [ 83.024476] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c8c0 (DMA) [ 83.024479] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.079399] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.079402] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.079406] xhci_hcd 0000:00:10.0: @5d22c470 5d22c8b0 00000000 01000000 01018001 [ 83.079408] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.079411] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.079412] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.079414] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.079416] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.079420] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560688 [ 83.079422] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.079425] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c8a0 (DMA) [ 83.079427] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c8b0 (DMA) [ 83.079428] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c8c0 (DMA) [ 83.079431] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c480 (DMA) [ 83.079434] xhci_hcd 0000:00:10.0: Giveback URB ffff88005c2fbe40, len = 31, status = 0 [ 83.079442] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.079444] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.079448] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c488, 4'hf); [ 83.079464] usb 6-1: skipped 1 descriptor after endpoint [ 83.079471] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.079474] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.079476] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c8d0 (DMA) [ 83.079478] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c8e0 (DMA) [ 83.079480] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c8f0 (DMA) [ 83.079483] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.094590] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.094593] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.094596] xhci_hcd 0000:00:10.0: @5d22c480 5d22c8d0 00000000 0d0000fb 01018001 [ 83.094598] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.094600] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.094602] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.094604] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.094606] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.094609] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560720 [ 83.094611] xhci_hcd 0000:00:10.0: WARN: short transfer on control ep [ 83.094613] xhci_hcd 0000:00:10.0: Waiting for status stage event [ 83.094615] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c490 (DMA) [ 83.094617] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.094619] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.094621] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.094623] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.094625] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.094627] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560736 [ 83.094629] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.094631] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c8d0 (DMA) [ 83.094633] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c8e0 (DMA) [ 83.094634] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c8f0 (DMA) [ 83.094636] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c4a0 (DMA) [ 83.094639] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a7573c0, len = 4, status = 0 [ 83.094647] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.094649] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.094654] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c4a8, 4'hf); [ 83.094666] usb 6-1: default language 0x0409 [ 83.094672] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.094674] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.094677] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c900 (DMA) [ 83.094679] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c910 (DMA) [ 83.094681] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c920 (DMA) [ 83.094684] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.109660] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.109664] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.109668] xhci_hcd 0000:00:10.0: @5d22c4a0 5d22c900 00000000 0d0000d9 01018001 [ 83.109671] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.109674] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.109675] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.109677] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.109680] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.109684] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560768 [ 83.109686] xhci_hcd 0000:00:10.0: WARN: short transfer on control ep [ 83.109688] xhci_hcd 0000:00:10.0: Waiting for status stage event [ 83.109691] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c4b0 (DMA) [ 83.109693] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.109695] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.109700] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c4b8, 4'hf); [ 83.109743] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.109744] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.109747] xhci_hcd 0000:00:10.0: @5d22c4b0 5d22c910 00000000 01000000 01018001 [ 83.109749] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.109752] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.109754] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.109755] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.109758] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.109760] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560784 [ 83.109762] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.109764] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c900 (DMA) [ 83.109766] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c910 (DMA) [ 83.109768] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c920 (DMA) [ 83.109770] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c4c0 (DMA) [ 83.109774] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a0859c0, len = 38, status = 0 [ 83.109789] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.109792] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.109796] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c4c8, 4'hf); [ 83.109822] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.109827] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.109830] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c930 (DMA) [ 83.109833] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c940 (DMA) [ 83.109835] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c950 (DMA) [ 83.109838] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.124930] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.124934] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.124937] xhci_hcd 0000:00:10.0: @5d22c4c0 5d22c930 00000000 0d0000e1 01018001 [ 83.124940] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.124942] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.124944] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.124946] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.124948] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.124952] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560816 [ 83.124954] xhci_hcd 0000:00:10.0: WARN: short transfer on control ep [ 83.124956] xhci_hcd 0000:00:10.0: Waiting for status stage event [ 83.124958] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c4d0 (DMA) [ 83.124960] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.124962] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.124967] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c4d8, 4'hf); [ 83.124996] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.124997] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.125000] xhci_hcd 0000:00:10.0: @5d22c4d0 5d22c940 00000000 01000000 01018001 [ 83.125002] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.125004] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.125005] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.125007] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.125009] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.125011] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560832 [ 83.125013] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.125015] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c930 (DMA) [ 83.125017] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c940 (DMA) [ 83.125019] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c950 (DMA) [ 83.125021] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c4e0 (DMA) [ 83.125024] xhci_hcd 0000:00:10.0: Giveback URB ffff88005bd7f180, len = 30, status = 0 [ 83.125032] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.125034] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.125039] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c4e8, 4'hf); [ 83.125050] usb 6-1: udev 2, busnum 6, minor = 641 [ 83.125052] usb 6-1: New USB device found, idVendor=2109, idProduct=0810 [ 83.125055] usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 83.125057] usb 6-1: Product: 4-Port USB 3.0 Hub [ 83.125058] usb 6-1: Manufacturer: VIA Labs, Inc. [ 83.125163] usb 6-1: usb_probe_device [ 83.125167] usb 6-1: configuration #1 chosen from 1 choice [ 83.125174] xhci_hcd 0000:00:10.0: Allocating ring at ffff88005a65a900 [ 83.125176] xhci_hcd 0000:00:10.0: Allocating priv segment structure at ffff88005badcf40 [ 83.125183] xhci_hcd 0000:00:10.0: // Allocating segment at ffff88005bf64000 (virtual) 0x5bf64000 (DMA) [ 83.125223] xhci_hcd 0000:00:10.0: Linking segment 0x5bf64000 to segment 0x5bf64000 (DMA) [ 83.125226] xhci_hcd 0000:00:10.0: Wrote link toggle flag to segment ffff88005badcf40 (virtual), 0x5bf64000 (DMA) [ 83.125229] usb 6-1: ep 0x81 - rounding interval to 32768 microframes [ 83.125231] xhci_hcd 0000:00:10.0: WARN no SS endpoint bMaxBurst [ 83.125235] xhci_hcd 0000:00:10.0: add ep 0x81, slot id 1, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x18400000 [ 83.125238] xhci_hcd 0000:00:10.0: xhci_check_bandwidth called for udev ffff88005bbc8000 [ 83.125240] xhci_hcd 0000:00:10.0: New Input Control Context: [ 83.125243] xhci_hcd 0000:00:10.0: @ffff88005a0d0000 (virt) @5a0d0000 (dma) 0x000000 - drop flags [ 83.125246] xhci_hcd 0000:00:10.0: @ffff88005a0d0004 (virt) @5a0d0004 (dma) 0x000009 - add flags [ 83.125249] xhci_hcd 0000:00:10.0: @ffff88005a0d0008 (virt) @5a0d0008 (dma) 0x000000 - rsvd2[0] [ 83.125252] xhci_hcd 0000:00:10.0: @ffff88005a0d000c (virt) @5a0d000c (dma) 0x000000 - rsvd2[1] [ 83.125255] xhci_hcd 0000:00:10.0: @ffff88005a0d0010 (virt) @5a0d0010 (dma) 0x000000 - rsvd2[2] [ 83.125257] xhci_hcd 0000:00:10.0: @ffff88005a0d0014 (virt) @5a0d0014 (dma) 0x000000 - rsvd2[3] [ 83.125260] xhci_hcd 0000:00:10.0: @ffff88005a0d0018 (virt) @5a0d0018 (dma) 0x000000 - rsvd2[4] [ 83.125263] xhci_hcd 0000:00:10.0: @ffff88005a0d001c (virt) @5a0d001c (dma) 0x000000 - rsvd2[5] [ 83.125265] xhci_hcd 0000:00:10.0: Slot Context: [ 83.125268] xhci_hcd 0000:00:10.0: @ffff88005a0d0020 (virt) @5a0d0020 (dma) 0x18400000 - dev_info [ 83.125271] xhci_hcd 0000:00:10.0: @ffff88005a0d0024 (virt) @5a0d0024 (dma) 0x010000 - dev_info2 [ 83.125273] xhci_hcd 0000:00:10.0: @ffff88005a0d0028 (virt) @5a0d0028 (dma) 0x000000 - tt_info [ 83.125276] xhci_hcd 0000:00:10.0: @ffff88005a0d002c (virt) @5a0d002c (dma) 0x000000 - dev_state [ 83.125279] xhci_hcd 0000:00:10.0: @ffff88005a0d0030 (virt) @5a0d0030 (dma) 0x000000 - rsvd[0] [ 83.125282] xhci_hcd 0000:00:10.0: @ffff88005a0d0034 (virt) @5a0d0034 (dma) 0x000000 - rsvd[1] [ 83.125285] xhci_hcd 0000:00:10.0: @ffff88005a0d0038 (virt) @5a0d0038 (dma) 0x000000 - rsvd[2] [ 83.125287] xhci_hcd 0000:00:10.0: @ffff88005a0d003c (virt) @5a0d003c (dma) 0x000000 - rsvd[3] [ 83.125290] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.125292] xhci_hcd 0000:00:10.0: @ffff88005a0d0040 (virt) @5a0d0040 (dma) 0x000000 - ep_info [ 83.125295] xhci_hcd 0000:00:10.0: @ffff88005a0d0044 (virt) @5a0d0044 (dma) 0x2000026 - ep_info2 [ 83.125297] xhci_hcd 0000:00:10.0: @ffff88005a0d0048 (virt) @5a0d0048 (dma) 0x5d22c801 - deq [ 83.125300] xhci_hcd 0000:00:10.0: @ffff88005a0d0050 (virt) @5a0d0050 (dma) 0x000000 - tx_info [ 83.125303] xhci_hcd 0000:00:10.0: @ffff88005a0d0054 (virt) @5a0d0054 (dma) 0x000000 - rsvd[0] [ 83.125306] xhci_hcd 0000:00:10.0: @ffff88005a0d0058 (virt) @5a0d0058 (dma) 0x000000 - rsvd[1] [ 83.125309] xhci_hcd 0000:00:10.0: @ffff88005a0d005c (virt) @5a0d005c (dma) 0x000000 - rsvd[2] [ 83.125311] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 83.125313] xhci_hcd 0000:00:10.0: @ffff88005a0d0060 (virt) @5a0d0060 (dma) 0x000000 - ep_info [ 83.125316] xhci_hcd 0000:00:10.0: @ffff88005a0d0064 (virt) @5a0d0064 (dma) 0x000000 - ep_info2 [ 83.125319] xhci_hcd 0000:00:10.0: @ffff88005a0d0068 (virt) @5a0d0068 (dma) 0x000000 - deq [ 83.125321] xhci_hcd 0000:00:10.0: @ffff88005a0d0070 (virt) @5a0d0070 (dma) 0x000000 - tx_info [ 83.125324] xhci_hcd 0000:00:10.0: @ffff88005a0d0074 (virt) @5a0d0074 (dma) 0x000000 - rsvd[0] [ 83.125327] xhci_hcd 0000:00:10.0: @ffff88005a0d0078 (virt) @5a0d0078 (dma) 0x000000 - rsvd[1] [ 83.125330] xhci_hcd 0000:00:10.0: @ffff88005a0d007c (virt) @5a0d007c (dma) 0x000000 - rsvd[2] [ 83.125332] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 83.125334] xhci_hcd 0000:00:10.0: @ffff88005a0d0080 (virt) @5a0d0080 (dma) 0x0f0000 - ep_info [ 83.125337] xhci_hcd 0000:00:10.0: @ffff88005a0d0084 (virt) @5a0d0084 (dma) 0x02003e - ep_info2 [ 83.125340] xhci_hcd 0000:00:10.0: @ffff88005a0d0088 (virt) @5a0d0088 (dma) 0x5bf64001 - deq [ 83.125343] xhci_hcd 0000:00:10.0: @ffff88005a0d0090 (virt) @5a0d0090 (dma) 0x020002 - tx_info [ 83.125345] xhci_hcd 0000:00:10.0: @ffff88005a0d0094 (virt) @5a0d0094 (dma) 0x000000 - rsvd[0] [ 83.125348] xhci_hcd 0000:00:10.0: @ffff88005a0d0098 (virt) @5a0d0098 (dma) 0x000000 - rsvd[1] [ 83.125351] xhci_hcd 0000:00:10.0: @ffff88005a0d009c (virt) @5a0d009c (dma) 0x000000 - rsvd[2] [ 83.125354] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.125357] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c030 (DMA) [ 83.125359] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.125398] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.125627] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.125630] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.125633] xhci_hcd 0000:00:10.0: @5d22c4e0 5d22c020 00000000 01000000 01008401 [ 83.125636] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.125639] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.125640] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.125643] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.125646] xhci_hcd 0000:00:10.0: Completed config ep cmd [ 83.125656] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c030 (DMA) [ 83.125658] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.125660] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c4f0 (DMA) [ 83.125662] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.125668] usb 6-1: Successful Endpoint Configure command [ 83.125672] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c4f8, 4'hf); [ 83.125676] xhci_hcd 0000:00:10.0: Output context after successful config ep cmd: [ 83.125679] xhci_hcd 0000:00:10.0: Slot Context: [ 83.125682] xhci_hcd 0000:00:10.0: @ffff88005a0cf000 (virt) @5a0cf000 (dma) 0x18400000 - dev_info [ 83.125685] xhci_hcd 0000:00:10.0: @ffff88005a0cf004 (virt) @5a0cf004 (dma) 0x010000 - dev_info2 [ 83.125688] xhci_hcd 0000:00:10.0: @ffff88005a0cf008 (virt) @5a0cf008 (dma) 0x000000 - tt_info [ 83.125691] xhci_hcd 0000:00:10.0: @ffff88005a0cf00c (virt) @5a0cf00c (dma) 0x18000001 - dev_state [ 83.125694] xhci_hcd 0000:00:10.0: @ffff88005a0cf010 (virt) @5a0cf010 (dma) 0x000000 - rsvd[0] [ 83.125697] xhci_hcd 0000:00:10.0: @ffff88005a0cf014 (virt) @5a0cf014 (dma) 0x000000 - rsvd[1] [ 83.125700] xhci_hcd 0000:00:10.0: @ffff88005a0cf018 (virt) @5a0cf018 (dma) 0x000000 - rsvd[2] [ 83.125702] xhci_hcd 0000:00:10.0: @ffff88005a0cf01c (virt) @5a0cf01c (dma) 0x000000 - rsvd[3] [ 83.125705] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.125707] xhci_hcd 0000:00:10.0: @ffff88005a0cf020 (virt) @5a0cf020 (dma) 0x000001 - ep_info [ 83.125710] xhci_hcd 0000:00:10.0: @ffff88005a0cf024 (virt) @5a0cf024 (dma) 0x2000026 - ep_info2 [ 83.125713] xhci_hcd 0000:00:10.0: @ffff88005a0cf028 (virt) @5a0cf028 (dma) 0x5d22c801 - deq [ 83.125716] xhci_hcd 0000:00:10.0: @ffff88005a0cf030 (virt) @5a0cf030 (dma) 0x000000 - tx_info [ 83.125718] xhci_hcd 0000:00:10.0: @ffff88005a0cf034 (virt) @5a0cf034 (dma) 0x000000 - rsvd[0] [ 83.125721] xhci_hcd 0000:00:10.0: @ffff88005a0cf038 (virt) @5a0cf038 (dma) 0x000000 - rsvd[1] [ 83.125724] xhci_hcd 0000:00:10.0: @ffff88005a0cf03c (virt) @5a0cf03c (dma) 0x000000 - rsvd[2] [ 83.125727] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 83.125729] xhci_hcd 0000:00:10.0: @ffff88005a0cf040 (virt) @5a0cf040 (dma) 0x000000 - ep_info [ 83.125731] xhci_hcd 0000:00:10.0: @ffff88005a0cf044 (virt) @5a0cf044 (dma) 0x000000 - ep_info2 [ 83.125734] xhci_hcd 0000:00:10.0: @ffff88005a0cf048 (virt) @5a0cf048 (dma) 0x000000 - deq [ 83.125737] xhci_hcd 0000:00:10.0: @ffff88005a0cf050 (virt) @5a0cf050 (dma) 0x000000 - tx_info [ 83.125740] xhci_hcd 0000:00:10.0: @ffff88005a0cf054 (virt) @5a0cf054 (dma) 0x000000 - rsvd[0] [ 83.125742] xhci_hcd 0000:00:10.0: @ffff88005a0cf058 (virt) @5a0cf058 (dma) 0x000000 - rsvd[1] [ 83.125745] xhci_hcd 0000:00:10.0: @ffff88005a0cf05c (virt) @5a0cf05c (dma) 0x000000 - rsvd[2] [ 83.125748] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 83.125750] xhci_hcd 0000:00:10.0: @ffff88005a0cf060 (virt) @5a0cf060 (dma) 0x0f0001 - ep_info [ 83.125752] xhci_hcd 0000:00:10.0: @ffff88005a0cf064 (virt) @5a0cf064 (dma) 0x02003e - ep_info2 [ 83.125755] xhci_hcd 0000:00:10.0: @ffff88005a0cf068 (virt) @5a0cf068 (dma) 0x5bf64001 - deq [ 83.125758] xhci_hcd 0000:00:10.0: @ffff88005a0cf070 (virt) @5a0cf070 (dma) 0x020002 - tx_info [ 83.125761] xhci_hcd 0000:00:10.0: @ffff88005a0cf074 (virt) @5a0cf074 (dma) 0x000000 - rsvd[0] [ 83.125763] xhci_hcd 0000:00:10.0: @ffff88005a0cf078 (virt) @5a0cf078 (dma) 0x000000 - rsvd[1] [ 83.125766] xhci_hcd 0000:00:10.0: @ffff88005a0cf07c (virt) @5a0cf07c (dma) 0x000000 - rsvd[2] [ 83.125776] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.125778] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.125782] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c960 (DMA) [ 83.125784] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c970 (DMA) [ 83.125789] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.130691] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.130694] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.130697] xhci_hcd 0000:00:10.0: @5d22c4f0 5d22c960 00000000 01000000 01018001 [ 83.130700] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.130702] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.130704] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.130706] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.130708] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.130711] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560864 [ 83.130713] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.130716] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c960 (DMA) [ 83.130718] xhci_hcd 0000:00:10.0: Ring deq = 0x5d22c970 (DMA) [ 83.130720] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c500 (DMA) [ 83.130723] xhci_hcd 0000:00:10.0: Giveback URB ffff88005bd7fa80, len = 0, status = 0 [ 83.130729] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.130731] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.130736] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c508, 4'hf); [ 83.130742] xhci_hcd 0000:00:10.0: Endpoint 0x81 not halted, refusing to reset. [ 83.130750] usb 6-1: adding 6-1:1.0 (config #1, interface 0) [ 83.130805] hub 6-1:1.0: usb_probe_interface [ 83.130808] hub 6-1:1.0: usb_probe_interface - got id [ 83.130812] hub 6-1:1.0: USB hub found [ 83.130819] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.130821] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.130824] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c980 (DMA) [ 83.130826] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c990 (DMA) [ 83.130828] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c9a0 (DMA) [ 83.130869] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.184375] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.184379] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.184382] xhci_hcd 0000:00:10.0: @5d22c500 5d22c980 00000000 0600000f 01018001 [ 83.184384] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.184387] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.184389] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.184391] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.184393] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.184395] xhci_hcd 0000:00:10.0: WARN: Stalled endpoint [ 83.184398] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560896 [ 83.184401] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.184403] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c040 (DMA) [ 83.184406] xhci_hcd 0000:00:10.0: Cleaning up stalled endpoint ring [ 83.184408] xhci_hcd 0000:00:10.0: Finding segment containing stopped TRB. [ 83.184409] xhci_hcd 0000:00:10.0: Finding endpoint context [ 83.184411] xhci_hcd 0000:00:10.0: Finding segment containing last TRB in TD. [ 83.184413] xhci_hcd 0000:00:10.0: New dequeue segment = ffff88005badcea0 (virtual) [ 83.184415] xhci_hcd 0000:00:10.0: New dequeue pointer = 0x5d22c9a0 (DMA) [ 83.184417] xhci_hcd 0000:00:10.0: Setting dequeue pointer in internal ring state. [ 83.184419] xhci_hcd 0000:00:10.0: Queueing new dequeue state [ 83.184421] xhci_hcd 0000:00:10.0: Set TR Deq Ptr cmd, new deq seg = ffff88005badcea0 (0x5d22c800 dma), new deq ptr = ffff88005d22c9a0 (0x5d22c9a0 dma), new cycle = 1 [ 83.184424] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.184426] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c050 (DMA) [ 83.184428] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.184431] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.184435] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c510 (DMA) [ 83.184439] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a14d840, len = 0, status = -32 [ 83.184444] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.184446] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.184451] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c518, 4'hf); [ 83.184486] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.184488] xhci_hcd 0000:00:10.0: Endpoint state = 0x3 [ 83.184491] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c9b0 (DMA) [ 83.184493] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c9c0 (DMA) [ 83.184495] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c9d0 (DMA) [ 83.184501] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.184503] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.184505] xhci_hcd 0000:00:10.0: @5d22c510 5d22c030 00000000 01000000 01008401 [ 83.184508] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.184510] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.184512] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.184514] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.184516] xhci_hcd 0000:00:10.0: Ignoring reset ep completion code of 1 [ 83.184519] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c040 (DMA) [ 83.184521] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.184523] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c520 (DMA) [ 83.184525] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.184530] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c528, 4'hf); [ 83.184559] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.184561] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.184563] xhci_hcd 0000:00:10.0: @5d22c520 5d22c040 00000000 01000000 01008401 [ 83.184566] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.184568] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.184570] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.184572] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.184575] xhci_hcd 0000:00:10.0: Successful Set TR Deq Ptr cmd, deq = @5d22c9a1 [ 83.184578] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.184581] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c050 (DMA) [ 83.184583] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.184585] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c530 (DMA) [ 83.184587] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.184591] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c538, 4'hf); [ 83.190006] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.190010] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.190013] xhci_hcd 0000:00:10.0: @5d22c530 5d22c9b0 00000000 0600000f 01018001 [ 83.190016] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.190018] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.190020] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.190022] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.190024] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.190026] xhci_hcd 0000:00:10.0: WARN: Stalled endpoint [ 83.190029] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560944 [ 83.190032] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.190034] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c060 (DMA) [ 83.190036] xhci_hcd 0000:00:10.0: Cleaning up stalled endpoint ring [ 83.190038] xhci_hcd 0000:00:10.0: Finding segment containing stopped TRB. [ 83.190040] xhci_hcd 0000:00:10.0: Finding endpoint context [ 83.190042] xhci_hcd 0000:00:10.0: Finding segment containing last TRB in TD. [ 83.190044] xhci_hcd 0000:00:10.0: New dequeue segment = ffff88005badcea0 (virtual) [ 83.190046] xhci_hcd 0000:00:10.0: New dequeue pointer = 0x5d22c9d0 (DMA) [ 83.190047] xhci_hcd 0000:00:10.0: Setting dequeue pointer in internal ring state. [ 83.190049] xhci_hcd 0000:00:10.0: Queueing new dequeue state [ 83.190052] xhci_hcd 0000:00:10.0: Set TR Deq Ptr cmd, new deq seg = ffff88005badcea0 (0x5d22c800 dma), new deq ptr = ffff88005d22c9d0 (0x5d22c9d0 dma), new cycle = 1 [ 83.190055] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.190057] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c070 (DMA) [ 83.190059] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.190062] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.190066] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c540 (DMA) [ 83.190069] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a718900, len = 0, status = -32 [ 83.190077] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.190079] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.190083] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c548, 4'hf); [ 83.190117] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 1, ep 0 [ 83.190119] xhci_hcd 0000:00:10.0: Endpoint state = 0x3 [ 83.190122] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c9e0 (DMA) [ 83.190123] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22c9f0 (DMA) [ 83.190125] xhci_hcd 0000:00:10.0: Ring enq = 0x5d22ca00 (DMA) [ 83.190132] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.190134] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.190136] xhci_hcd 0000:00:10.0: @5d22c540 5d22c050 00000000 01000000 01008401 [ 83.190138] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.190140] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.190142] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.190144] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.190146] xhci_hcd 0000:00:10.0: Ignoring reset ep completion code of 1 [ 83.190148] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c060 (DMA) [ 83.190150] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.190152] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c550 (DMA) [ 83.190154] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.190158] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c558, 4'hf); [ 83.190189] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.190191] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.190193] xhci_hcd 0000:00:10.0: @5d22c550 5d22c060 00000000 01000000 01008401 [ 83.190195] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.190197] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.190199] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.190200] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.190203] xhci_hcd 0000:00:10.0: Successful Set TR Deq Ptr cmd, deq = @5d22c9d1 [ 83.190206] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918804, 32'h1, 4'hf); [ 83.190208] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c070 (DMA) [ 83.190210] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.190212] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c560 (DMA) [ 83.190214] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.190218] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c568, 4'hf); [ 83.195702] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.195706] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.195709] xhci_hcd 0000:00:10.0: @5d22c560 5d22c9e0 00000000 0600000f 01018001 [ 83.195711] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.195714] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.195715] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.195717] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.195719] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.195722] xhci_hcd 0000:00:10.0: WARN: Stalled endpoint [ 83.195725] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1562560992 [ 83.195728] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.195730] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c080 (DMA) [ 83.195732] xhci_hcd 0000:00:10.0: Cleaning up stalled endpoint ring [ 83.195734] xhci_hcd 0000:00:10.0: Finding segment containing stopped TRB. [ 83.195736] xhci_hcd 0000:00:10.0: Finding endpoint context [ 83.195738] xhci_hcd 0000:00:10.0: Finding segment containing last TRB in TD. [ 83.195740] xhci_hcd 0000:00:10.0: New dequeue segment = ffff88005badcea0 (virtual) [ 83.195742] xhci_hcd 0000:00:10.0: New dequeue pointer = 0x5d22ca00 (DMA) [ 83.195743] xhci_hcd 0000:00:10.0: Setting dequeue pointer in internal ring state. [ 83.195745] xhci_hcd 0000:00:10.0: Queueing new dequeue state [ 83.195748] xhci_hcd 0000:00:10.0: Set TR Deq Ptr cmd, new deq seg = ffff88005badcea0 (0x5d22c800 dma), new deq ptr = ffff88005d22ca00 (0x5d22ca00 dma), new cycle = 1 [ 83.195751] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.195752] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c090 (DMA) [ 83.195754] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.195757] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.195761] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c570 (DMA) [ 83.195765] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c180, len = 0, status = -32 [ 83.195774] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.195776] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.195781] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c578, 4'hf); [ 83.195792] hub 6-1:1.0: config failed, can't read hub descriptor (err -22) [ 83.195826] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.195828] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.195831] xhci_hcd 0000:00:10.0: @5d22c570 5d22c070 00000000 01000000 01008401 [ 83.195833] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.195835] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.195837] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.195839] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.195841] xhci_hcd 0000:00:10.0: Ignoring reset ep completion code of 1 [ 83.195843] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c080 (DMA) [ 83.195845] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.195847] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c580 (DMA) [ 83.195849] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.195853] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c588, 4'hf); [ 83.195885] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.195886] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.195889] xhci_hcd 0000:00:10.0: @5d22c580 5d22c080 00000000 01000000 01008401 [ 83.195891] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.195894] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.195896] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.195898] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.195900] xhci_hcd 0000:00:10.0: Successful Set TR Deq Ptr cmd, deq = @5d22ca01 [ 83.195902] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c090 (DMA) [ 83.195904] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.195907] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c590 (DMA) [ 83.195909] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.195913] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c598, 4'hf); [ 83.195933] xhci_hcd 0000:00:10.0: get port status, actual port 2 status = 0x2e1 [ 83.195935] xhci_hcd 0000:00:10.0: Get port status returned 0x101 [ 83.195939] hub 6-0:1.0: port 3, status 0101, change 0000, 12 Mb/s [ 83.195943] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.195945] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c0a0 (DMA) [ 83.195947] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.195950] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.195989] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.195991] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.195994] xhci_hcd 0000:00:10.0: @5d22c590 5d22c090 00000000 01000000 02008401 [ 83.195996] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.195998] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.196000] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.196002] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.196006] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c0a0 (DMA) [ 83.196008] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.196010] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c5a0 (DMA) [ 83.196012] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.196016] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c5a8, 4'hf); [ 83.196043] xhci_hcd 0000:00:10.0: Slot 2 output ctx = 0x5a161000 (dma) [ 83.196047] xhci_hcd 0000:00:10.0: Slot 2 input ctx = 0x5a162000 (dma) [ 83.196050] xhci_hcd 0000:00:10.0: Allocating ring at ffff88005a65a360 [ 83.196052] xhci_hcd 0000:00:10.0: Allocating priv segment structure at ffff88005badcdc0 [ 83.196055] xhci_hcd 0000:00:10.0: // Allocating segment at ffff88005bf64400 (virtual) 0x5bf64400 (DMA) [ 83.196059] xhci_hcd 0000:00:10.0: Linking segment 0x5bf64400 to segment 0x5bf64400 (DMA) [ 83.196062] xhci_hcd 0000:00:10.0: Wrote link toggle flag to segment ffff88005badcdc0 (virtual), 0x5bf64400 (DMA) [ 83.196066] xhci_hcd 0000:00:10.0: Set slot id 2 dcbaa entry ffff88005d984010 to 0x5a161000 [ 83.196073] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918440, 32'h2f1, 4'hf); [ 83.196077] xhci_hcd 0000:00:10.0: set port reset, actual port 2 status = 0x331 [ 83.246496] xhci_hcd 0000:00:10.0: op reg status = 00000018 [ 83.246500] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.246503] xhci_hcd 0000:00:10.0: @5d22c5a0 03000000 00000000 01000000 00008801 [ 83.246506] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h18, 4'hf); [ 83.246509] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.246510] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.246512] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_port_status [ 83.246514] xhci_hcd 0000:00:10.0: Port Status Change Event for port 3 [ 83.246518] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c5b0 (DMA) [ 83.246525] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_port_status [ 83.246527] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.246531] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c5b8, 4'hf); [ 83.250161] xhci_hcd 0000:00:10.0: get port status, actual port 2 status = 0x200e03 [ 83.250165] xhci_hcd 0000:00:10.0: Get port status returned 0x503 [ 83.310087] xhci_hcd 0000:00:10.0: Resetting device with slot ID 2 [ 83.310092] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.310095] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c0b0 (DMA) [ 83.310097] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.310100] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.310138] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.310140] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.310143] xhci_hcd 0000:00:10.0: @5d22c5b0 5d22c0a0 00000000 13000000 02008401 [ 83.310146] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.310148] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.310150] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.310152] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.310155] xhci_hcd 0000:00:10.0: Completed reset device command. [ 83.310158] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c0b0 (DMA) [ 83.310160] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.310163] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c5c0 (DMA) [ 83.310165] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.310169] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c5c8, 4'hf); [ 83.310174] xhci_hcd 0000:00:10.0: Can't reset device (slot ID 2) in enabled/disabled state [ 83.310176] xhci_hcd 0000:00:10.0: Not freeing device rings. [ 83.310184] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918440, 32'h200e01, 4'hf); [ 83.310189] xhci_hcd 0000:00:10.0: clear port reset change, actual port 2 status = 0xe03 [ 83.310195] usb 6-3: new high speed USB device using xhci_hcd and address 3 [ 83.310198] xhci_hcd 0000:00:10.0: Set root hub portnum to 3 [ 83.310201] xhci_hcd 0000:00:10.0: udev->tt = (null) [ 83.310203] xhci_hcd 0000:00:10.0: udev->ttport = 0x0 [ 83.310205] xhci_hcd 0000:00:10.0: Slot ID 2 Input Context: [ 83.310208] xhci_hcd 0000:00:10.0: @ffff88005a162000 (virt) @5a162000 (dma) 0x000000 - drop flags [ 83.310211] xhci_hcd 0000:00:10.0: @ffff88005a162004 (virt) @5a162004 (dma) 0x000003 - add flags [ 83.310214] xhci_hcd 0000:00:10.0: @ffff88005a162008 (virt) @5a162008 (dma) 0x000000 - rsvd2[0] [ 83.310217] xhci_hcd 0000:00:10.0: @ffff88005a16200c (virt) @5a16200c (dma) 0x000000 - rsvd2[1] [ 83.310219] xhci_hcd 0000:00:10.0: @ffff88005a162010 (virt) @5a162010 (dma) 0x000000 - rsvd2[2] [ 83.310222] xhci_hcd 0000:00:10.0: @ffff88005a162014 (virt) @5a162014 (dma) 0x000000 - rsvd2[3] [ 83.310225] xhci_hcd 0000:00:10.0: @ffff88005a162018 (virt) @5a162018 (dma) 0x000000 - rsvd2[4] [ 83.310228] xhci_hcd 0000:00:10.0: @ffff88005a16201c (virt) @5a16201c (dma) 0x000000 - rsvd2[5] [ 83.310230] xhci_hcd 0000:00:10.0: Slot Context: [ 83.310232] xhci_hcd 0000:00:10.0: @ffff88005a162020 (virt) @5a162020 (dma) 0x8300000 - dev_info [ 83.310235] xhci_hcd 0000:00:10.0: @ffff88005a162024 (virt) @5a162024 (dma) 0x030000 - dev_info2 [ 83.310238] xhci_hcd 0000:00:10.0: @ffff88005a162028 (virt) @5a162028 (dma) 0x000000 - tt_info [ 83.310241] xhci_hcd 0000:00:10.0: @ffff88005a16202c (virt) @5a16202c (dma) 0x000000 - dev_state [ 83.310244] xhci_hcd 0000:00:10.0: @ffff88005a162030 (virt) @5a162030 (dma) 0x000000 - rsvd[0] [ 83.310246] xhci_hcd 0000:00:10.0: @ffff88005a162034 (virt) @5a162034 (dma) 0x000000 - rsvd[1] [ 83.310249] xhci_hcd 0000:00:10.0: @ffff88005a162038 (virt) @5a162038 (dma) 0x000000 - rsvd[2] [ 83.310252] xhci_hcd 0000:00:10.0: @ffff88005a16203c (virt) @5a16203c (dma) 0x000000 - rsvd[3] [ 83.310254] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.310257] xhci_hcd 0000:00:10.0: @ffff88005a162040 (virt) @5a162040 (dma) 0x000000 - ep_info [ 83.310259] xhci_hcd 0000:00:10.0: @ffff88005a162044 (virt) @5a162044 (dma) 0x400026 - ep_info2 [ 83.310262] xhci_hcd 0000:00:10.0: @ffff88005a162048 (virt) @5a162048 (dma) 0x5bf64401 - deq [ 83.310265] xhci_hcd 0000:00:10.0: @ffff88005a162050 (virt) @5a162050 (dma) 0x000000 - tx_info [ 83.310268] xhci_hcd 0000:00:10.0: @ffff88005a162054 (virt) @5a162054 (dma) 0x000000 - rsvd[0] [ 83.310270] xhci_hcd 0000:00:10.0: @ffff88005a162058 (virt) @5a162058 (dma) 0x000000 - rsvd[1] [ 83.310273] xhci_hcd 0000:00:10.0: @ffff88005a16205c (virt) @5a16205c (dma) 0x000000 - rsvd[2] [ 83.310276] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 83.310278] xhci_hcd 0000:00:10.0: @ffff88005a162060 (virt) @5a162060 (dma) 0x000000 - ep_info [ 83.310281] xhci_hcd 0000:00:10.0: @ffff88005a162064 (virt) @5a162064 (dma) 0x000000 - ep_info2 [ 83.310283] xhci_hcd 0000:00:10.0: @ffff88005a162068 (virt) @5a162068 (dma) 0x000000 - deq [ 83.310286] xhci_hcd 0000:00:10.0: @ffff88005a162070 (virt) @5a162070 (dma) 0x000000 - tx_info [ 83.310289] xhci_hcd 0000:00:10.0: @ffff88005a162074 (virt) @5a162074 (dma) 0x000000 - rsvd[0] [ 83.310292] xhci_hcd 0000:00:10.0: @ffff88005a162078 (virt) @5a162078 (dma) 0x000000 - rsvd[1] [ 83.310294] xhci_hcd 0000:00:10.0: @ffff88005a16207c (virt) @5a16207c (dma) 0x000000 - rsvd[2] [ 83.310297] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 83.310299] xhci_hcd 0000:00:10.0: @ffff88005a162080 (virt) @5a162080 (dma) 0x000000 - ep_info [ 83.310302] xhci_hcd 0000:00:10.0: @ffff88005a162084 (virt) @5a162084 (dma) 0x000000 - ep_info2 [ 83.310304] xhci_hcd 0000:00:10.0: @ffff88005a162088 (virt) @5a162088 (dma) 0x000000 - deq [ 83.310307] xhci_hcd 0000:00:10.0: @ffff88005a162090 (virt) @5a162090 (dma) 0x000000 - tx_info [ 83.310310] xhci_hcd 0000:00:10.0: @ffff88005a162094 (virt) @5a162094 (dma) 0x000000 - rsvd[0] [ 83.310312] xhci_hcd 0000:00:10.0: @ffff88005a162098 (virt) @5a162098 (dma) 0x000000 - rsvd[1] [ 83.310315] xhci_hcd 0000:00:10.0: @ffff88005a16209c (virt) @5a16209c (dma) 0x000000 - rsvd[2] [ 83.310318] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.310320] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c0c0 (DMA) [ 83.310322] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.310360] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.310521] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.310525] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.310527] xhci_hcd 0000:00:10.0: @5d22c5c0 5d22c0b0 00000000 01000000 02008401 [ 83.310530] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.310532] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.310534] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.310536] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.310544] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c0c0 (DMA) [ 83.310546] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.310548] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c5d0 (DMA) [ 83.310550] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.310554] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c5d8, 4'hf); [ 83.310564] xhci_hcd 0000:00:10.0: Successful Address Device command [ 83.310568] xhci_hcd 0000:00:10.0: Op regs DCBAA ptr = 0x0000005d984000 [ 83.310571] xhci_hcd 0000:00:10.0: Slot ID 2 dcbaa entry @ffff88005d984010 = 0x0000005a161000 [ 83.310573] xhci_hcd 0000:00:10.0: Output Context DMA address = 0x5a161000 [ 83.310575] xhci_hcd 0000:00:10.0: Slot ID 2 Input Context: [ 83.310578] xhci_hcd 0000:00:10.0: @ffff88005a162000 (virt) @5a162000 (dma) 0x000000 - drop flags [ 83.310580] xhci_hcd 0000:00:10.0: @ffff88005a162004 (virt) @5a162004 (dma) 0x000003 - add flags [ 83.310583] xhci_hcd 0000:00:10.0: @ffff88005a162008 (virt) @5a162008 (dma) 0x000000 - rsvd2[0] [ 83.310586] xhci_hcd 0000:00:10.0: @ffff88005a16200c (virt) @5a16200c (dma) 0x000000 - rsvd2[1] [ 83.310588] xhci_hcd 0000:00:10.0: @ffff88005a162010 (virt) @5a162010 (dma) 0x000000 - rsvd2[2] [ 83.310590] xhci_hcd 0000:00:10.0: @ffff88005a162014 (virt) @5a162014 (dma) 0x000000 - rsvd2[3] [ 83.310593] xhci_hcd 0000:00:10.0: @ffff88005a162018 (virt) @5a162018 (dma) 0x000000 - rsvd2[4] [ 83.310595] xhci_hcd 0000:00:10.0: @ffff88005a16201c (virt) @5a16201c (dma) 0x000000 - rsvd2[5] [ 83.310598] xhci_hcd 0000:00:10.0: Slot Context: [ 83.310600] xhci_hcd 0000:00:10.0: @ffff88005a162020 (virt) @5a162020 (dma) 0x8300000 - dev_info [ 83.310602] xhci_hcd 0000:00:10.0: @ffff88005a162024 (virt) @5a162024 (dma) 0x030000 - dev_info2 [ 83.310605] xhci_hcd 0000:00:10.0: @ffff88005a162028 (virt) @5a162028 (dma) 0x000000 - tt_info [ 83.310607] xhci_hcd 0000:00:10.0: @ffff88005a16202c (virt) @5a16202c (dma) 0x000000 - dev_state [ 83.310610] xhci_hcd 0000:00:10.0: @ffff88005a162030 (virt) @5a162030 (dma) 0x000000 - rsvd[0] [ 83.310612] xhci_hcd 0000:00:10.0: @ffff88005a162034 (virt) @5a162034 (dma) 0x000000 - rsvd[1] [ 83.310615] xhci_hcd 0000:00:10.0: @ffff88005a162038 (virt) @5a162038 (dma) 0x000000 - rsvd[2] [ 83.310617] xhci_hcd 0000:00:10.0: @ffff88005a16203c (virt) @5a16203c (dma) 0x000000 - rsvd[3] [ 83.310619] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.310621] xhci_hcd 0000:00:10.0: @ffff88005a162040 (virt) @5a162040 (dma) 0x000000 - ep_info [ 83.310624] xhci_hcd 0000:00:10.0: @ffff88005a162044 (virt) @5a162044 (dma) 0x400026 - ep_info2 [ 83.310626] xhci_hcd 0000:00:10.0: @ffff88005a162048 (virt) @5a162048 (dma) 0x5bf64401 - deq [ 83.310628] xhci_hcd 0000:00:10.0: @ffff88005a162050 (virt) @5a162050 (dma) 0x000000 - tx_info [ 83.310631] xhci_hcd 0000:00:10.0: @ffff88005a162054 (virt) @5a162054 (dma) 0x000000 - rsvd[0] [ 83.310633] xhci_hcd 0000:00:10.0: @ffff88005a162058 (virt) @5a162058 (dma) 0x000000 - rsvd[1] [ 83.310636] xhci_hcd 0000:00:10.0: @ffff88005a16205c (virt) @5a16205c (dma) 0x000000 - rsvd[2] [ 83.310638] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 83.310640] xhci_hcd 0000:00:10.0: @ffff88005a162060 (virt) @5a162060 (dma) 0x000000 - ep_info [ 83.310642] xhci_hcd 0000:00:10.0: @ffff88005a162064 (virt) @5a162064 (dma) 0x000000 - ep_info2 [ 83.310645] xhci_hcd 0000:00:10.0: @ffff88005a162068 (virt) @5a162068 (dma) 0x000000 - deq [ 83.310647] xhci_hcd 0000:00:10.0: @ffff88005a162070 (virt) @5a162070 (dma) 0x000000 - tx_info [ 83.310649] xhci_hcd 0000:00:10.0: @ffff88005a162074 (virt) @5a162074 (dma) 0x000000 - rsvd[0] [ 83.310652] xhci_hcd 0000:00:10.0: @ffff88005a162078 (virt) @5a162078 (dma) 0x000000 - rsvd[1] [ 83.310654] xhci_hcd 0000:00:10.0: @ffff88005a16207c (virt) @5a16207c (dma) 0x000000 - rsvd[2] [ 83.310656] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 83.310658] xhci_hcd 0000:00:10.0: @ffff88005a162080 (virt) @5a162080 (dma) 0x000000 - ep_info [ 83.310661] xhci_hcd 0000:00:10.0: @ffff88005a162084 (virt) @5a162084 (dma) 0x000000 - ep_info2 [ 83.310663] xhci_hcd 0000:00:10.0: @ffff88005a162088 (virt) @5a162088 (dma) 0x000000 - deq [ 83.310666] xhci_hcd 0000:00:10.0: @ffff88005a162090 (virt) @5a162090 (dma) 0x000000 - tx_info [ 83.310668] xhci_hcd 0000:00:10.0: @ffff88005a162094 (virt) @5a162094 (dma) 0x000000 - rsvd[0] [ 83.310670] xhci_hcd 0000:00:10.0: @ffff88005a162098 (virt) @5a162098 (dma) 0x000000 - rsvd[1] [ 83.310673] xhci_hcd 0000:00:10.0: @ffff88005a16209c (virt) @5a16209c (dma) 0x000000 - rsvd[2] [ 83.310675] xhci_hcd 0000:00:10.0: Slot ID 2 Output Context: [ 83.310677] xhci_hcd 0000:00:10.0: Slot Context: [ 83.310679] xhci_hcd 0000:00:10.0: @ffff88005a161000 (virt) @5a161000 (dma) 0x8300000 - dev_info [ 83.310682] xhci_hcd 0000:00:10.0: @ffff88005a161004 (virt) @5a161004 (dma) 0x030000 - dev_info2 [ 83.310684] xhci_hcd 0000:00:10.0: @ffff88005a161008 (virt) @5a161008 (dma) 0x000000 - tt_info [ 83.310687] xhci_hcd 0000:00:10.0: @ffff88005a16100c (virt) @5a16100c (dma) 0x10000002 - dev_state [ 83.310690] xhci_hcd 0000:00:10.0: @ffff88005a161010 (virt) @5a161010 (dma) 0x000000 - rsvd[0] [ 83.310693] xhci_hcd 0000:00:10.0: @ffff88005a161014 (virt) @5a161014 (dma) 0x000000 - rsvd[1] [ 83.310695] xhci_hcd 0000:00:10.0: @ffff88005a161018 (virt) @5a161018 (dma) 0x000000 - rsvd[2] [ 83.310698] xhci_hcd 0000:00:10.0: @ffff88005a16101c (virt) @5a16101c (dma) 0x000000 - rsvd[3] [ 83.310700] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.310703] xhci_hcd 0000:00:10.0: @ffff88005a161020 (virt) @5a161020 (dma) 0x000001 - ep_info [ 83.310705] xhci_hcd 0000:00:10.0: @ffff88005a161024 (virt) @5a161024 (dma) 0x400026 - ep_info2 [ 83.310708] xhci_hcd 0000:00:10.0: @ffff88005a161028 (virt) @5a161028 (dma) 0x5bf64401 - deq [ 83.310711] xhci_hcd 0000:00:10.0: @ffff88005a161030 (virt) @5a161030 (dma) 0x000000 - tx_info [ 83.310713] xhci_hcd 0000:00:10.0: @ffff88005a161034 (virt) @5a161034 (dma) 0x000000 - rsvd[0] [ 83.310716] xhci_hcd 0000:00:10.0: @ffff88005a161038 (virt) @5a161038 (dma) 0x000000 - rsvd[1] [ 83.310719] xhci_hcd 0000:00:10.0: @ffff88005a16103c (virt) @5a16103c (dma) 0x000000 - rsvd[2] [ 83.310721] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 83.310723] xhci_hcd 0000:00:10.0: @ffff88005a161040 (virt) @5a161040 (dma) 0x000000 - ep_info [ 83.310726] xhci_hcd 0000:00:10.0: @ffff88005a161044 (virt) @5a161044 (dma) 0x000000 - ep_info2 [ 83.310729] xhci_hcd 0000:00:10.0: @ffff88005a161048 (virt) @5a161048 (dma) 0x000000 - deq [ 83.310731] xhci_hcd 0000:00:10.0: @ffff88005a161050 (virt) @5a161050 (dma) 0x000000 - tx_info [ 83.310734] xhci_hcd 0000:00:10.0: @ffff88005a161054 (virt) @5a161054 (dma) 0x000000 - rsvd[0] [ 83.310737] xhci_hcd 0000:00:10.0: @ffff88005a161058 (virt) @5a161058 (dma) 0x000000 - rsvd[1] [ 83.310740] xhci_hcd 0000:00:10.0: @ffff88005a16105c (virt) @5a16105c (dma) 0x000000 - rsvd[2] [ 83.310742] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 83.310744] xhci_hcd 0000:00:10.0: @ffff88005a161060 (virt) @5a161060 (dma) 0x000000 - ep_info [ 83.310747] xhci_hcd 0000:00:10.0: @ffff88005a161064 (virt) @5a161064 (dma) 0x000000 - ep_info2 [ 83.310749] xhci_hcd 0000:00:10.0: @ffff88005a161068 (virt) @5a161068 (dma) 0x000000 - deq [ 83.310752] xhci_hcd 0000:00:10.0: @ffff88005a161070 (virt) @5a161070 (dma) 0x000000 - tx_info [ 83.310755] xhci_hcd 0000:00:10.0: @ffff88005a161074 (virt) @5a161074 (dma) 0x000000 - rsvd[0] [ 83.310758] xhci_hcd 0000:00:10.0: @ffff88005a161078 (virt) @5a161078 (dma) 0x000000 - rsvd[1] [ 83.310760] xhci_hcd 0000:00:10.0: @ffff88005a16107c (virt) @5a16107c (dma) 0x000000 - rsvd[2] [ 83.310763] xhci_hcd 0000:00:10.0: Internal device address = 3 [ 83.330156] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.330160] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.330163] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64410 (DMA) [ 83.330165] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64420 (DMA) [ 83.330167] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64430 (DMA) [ 83.330170] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.330544] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.330547] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.330550] xhci_hcd 0000:00:10.0: @5d22c5d0 5bf64420 00000000 01000000 02018001 [ 83.330552] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.330555] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.330556] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.330558] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.330560] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.330564] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542865952 [ 83.330566] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.330569] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64410 (DMA) [ 83.330570] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64420 (DMA) [ 83.330572] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64430 (DMA) [ 83.330574] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c5e0 (DMA) [ 83.330577] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c840, len = 8, status = 0 [ 83.330585] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.330587] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.330592] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c5e8, 4'hf); [ 83.330608] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.330610] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.330613] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64440 (DMA) [ 83.330615] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64450 (DMA) [ 83.330617] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64460 (DMA) [ 83.330620] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.331043] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.331047] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.331049] xhci_hcd 0000:00:10.0: @5d22c5e0 5bf64450 00000000 01000000 02018001 [ 83.331052] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.331054] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.331056] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.331058] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.331060] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.331063] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866000 [ 83.331065] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.331068] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64440 (DMA) [ 83.331069] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64450 (DMA) [ 83.331071] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64460 (DMA) [ 83.331073] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c5f0 (DMA) [ 83.331076] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c840, len = 18, status = 0 [ 83.331085] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.331087] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.331091] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c5f8, 4'hf); [ 83.331110] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.331113] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.331115] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64470 (DMA) [ 83.331117] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64480 (DMA) [ 83.331119] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64490 (DMA) [ 83.331122] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.331544] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.331547] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.331550] xhci_hcd 0000:00:10.0: @5d22c5f0 5bf64480 00000000 01000000 02018001 [ 83.331552] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.331554] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.331556] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.331558] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.331560] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.331563] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866048 [ 83.331565] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.331568] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64470 (DMA) [ 83.331570] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64480 (DMA) [ 83.331571] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64490 (DMA) [ 83.331573] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c600 (DMA) [ 83.331576] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c840, len = 9, status = 0 [ 83.331585] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.331587] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.331591] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c608, 4'hf); [ 83.331607] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.331609] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.331612] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf644a0 (DMA) [ 83.331614] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf644b0 (DMA) [ 83.331615] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf644c0 (DMA) [ 83.331619] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.332045] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.332048] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.332051] xhci_hcd 0000:00:10.0: @5d22c600 5bf644b0 00000000 01000000 02018001 [ 83.332053] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.332055] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332057] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.332059] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.332061] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.332064] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866096 [ 83.332066] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.332069] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf644a0 (DMA) [ 83.332070] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf644b0 (DMA) [ 83.332072] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf644c0 (DMA) [ 83.332074] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c610 (DMA) [ 83.332077] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c840, len = 25, status = 0 [ 83.332086] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.332087] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332092] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c618, 4'hf); [ 83.332111] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.332113] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.332116] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf644d0 (DMA) [ 83.332117] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf644e0 (DMA) [ 83.332119] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf644f0 (DMA) [ 83.332122] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.332420] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.332423] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.332426] xhci_hcd 0000:00:10.0: @5d22c610 5bf644d0 00000000 0d0000fb 02018001 [ 83.332428] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.332430] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332432] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.332434] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.332436] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.332439] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866128 [ 83.332441] xhci_hcd 0000:00:10.0: WARN: short transfer on control ep [ 83.332443] xhci_hcd 0000:00:10.0: Waiting for status stage event [ 83.332445] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c620 (DMA) [ 83.332447] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.332449] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332454] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c628, 4'hf); [ 83.332486] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.332488] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.332490] xhci_hcd 0000:00:10.0: @5d22c620 5bf644e0 00000000 01000000 02018001 [ 83.332492] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.332494] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332496] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.332497] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.332499] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.332501] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866144 [ 83.332503] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.332505] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf644d0 (DMA) [ 83.332507] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf644e0 (DMA) [ 83.332509] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf644f0 (DMA) [ 83.332511] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c630 (DMA) [ 83.332514] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c840, len = 4, status = 0 [ 83.332522] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.332524] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332528] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c638, 4'hf); [ 83.332537] usb 6-3: default language 0x0409 [ 83.332543] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.332545] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.332548] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64500 (DMA) [ 83.332550] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64510 (DMA) [ 83.332552] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64520 (DMA) [ 83.332555] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.332759] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.332762] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.332765] xhci_hcd 0000:00:10.0: @5d22c630 5bf64500 00000000 0d0000e9 02018001 [ 83.332767] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.332769] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332771] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.332773] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.332775] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.332779] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866176 [ 83.332781] xhci_hcd 0000:00:10.0: WARN: short transfer on control ep [ 83.332783] xhci_hcd 0000:00:10.0: Waiting for status stage event [ 83.332785] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c640 (DMA) [ 83.332787] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.332789] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332793] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c648, 4'hf); [ 83.332873] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.332877] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.332879] xhci_hcd 0000:00:10.0: @5d22c640 5bf64510 00000000 01000000 02018001 [ 83.332881] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.332884] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332886] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.332887] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.332889] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.332893] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866192 [ 83.332895] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.332897] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64500 (DMA) [ 83.332899] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64510 (DMA) [ 83.332901] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64520 (DMA) [ 83.332903] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c650 (DMA) [ 83.332906] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c840, len = 22, status = 0 [ 83.332914] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.332916] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.332920] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c658, 4'hf); [ 83.332934] usb 6-3: udev 3, busnum 6, minor = 642 [ 83.332936] usb 6-3: New USB device found, idVendor=2109, idProduct=3431 [ 83.332938] usb 6-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0 [ 83.332940] usb 6-3: Product: USB2.0 Hub [ 83.333049] usb 6-3: usb_probe_device [ 83.333052] usb 6-3: configuration #1 chosen from 1 choice [ 83.333059] xhci_hcd 0000:00:10.0: Allocating ring at ffff88005a65a120 [ 83.333061] xhci_hcd 0000:00:10.0: Allocating priv segment structure at ffff88005badce00 [ 83.333065] xhci_hcd 0000:00:10.0: // Allocating segment at ffff88005bf64800 (virtual) 0x5bf64800 (DMA) [ 83.333104] xhci_hcd 0000:00:10.0: Linking segment 0x5bf64800 to segment 0x5bf64800 (DMA) [ 83.333107] xhci_hcd 0000:00:10.0: Wrote link toggle flag to segment ffff88005badce00 (virtual), 0x5bf64800 (DMA) [ 83.333110] usb 6-3: ep 0x81 - rounding interval to 2048 microframes [ 83.333114] xhci_hcd 0000:00:10.0: add ep 0x81, slot id 2, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x18300000 [ 83.333117] xhci_hcd 0000:00:10.0: xhci_check_bandwidth called for udev ffff88005bde7000 [ 83.333119] xhci_hcd 0000:00:10.0: New Input Control Context: [ 83.333122] xhci_hcd 0000:00:10.0: @ffff88005a162000 (virt) @5a162000 (dma) 0x000000 - drop flags [ 83.333125] xhci_hcd 0000:00:10.0: @ffff88005a162004 (virt) @5a162004 (dma) 0x000009 - add flags [ 83.333128] xhci_hcd 0000:00:10.0: @ffff88005a162008 (virt) @5a162008 (dma) 0x000000 - rsvd2[0] [ 83.333130] xhci_hcd 0000:00:10.0: @ffff88005a16200c (virt) @5a16200c (dma) 0x000000 - rsvd2[1] [ 83.333133] xhci_hcd 0000:00:10.0: @ffff88005a162010 (virt) @5a162010 (dma) 0x000000 - rsvd2[2] [ 83.333136] xhci_hcd 0000:00:10.0: @ffff88005a162014 (virt) @5a162014 (dma) 0x000000 - rsvd2[3] [ 83.333139] xhci_hcd 0000:00:10.0: @ffff88005a162018 (virt) @5a162018 (dma) 0x000000 - rsvd2[4] [ 83.333141] xhci_hcd 0000:00:10.0: @ffff88005a16201c (virt) @5a16201c (dma) 0x000000 - rsvd2[5] [ 83.333144] xhci_hcd 0000:00:10.0: Slot Context: [ 83.333146] xhci_hcd 0000:00:10.0: @ffff88005a162020 (virt) @5a162020 (dma) 0x18300000 - dev_info [ 83.333149] xhci_hcd 0000:00:10.0: @ffff88005a162024 (virt) @5a162024 (dma) 0x030000 - dev_info2 [ 83.333151] xhci_hcd 0000:00:10.0: @ffff88005a162028 (virt) @5a162028 (dma) 0x000000 - tt_info [ 83.333154] xhci_hcd 0000:00:10.0: @ffff88005a16202c (virt) @5a16202c (dma) 0x000000 - dev_state [ 83.333157] xhci_hcd 0000:00:10.0: @ffff88005a162030 (virt) @5a162030 (dma) 0x000000 - rsvd[0] [ 83.333160] xhci_hcd 0000:00:10.0: @ffff88005a162034 (virt) @5a162034 (dma) 0x000000 - rsvd[1] [ 83.333162] xhci_hcd 0000:00:10.0: @ffff88005a162038 (virt) @5a162038 (dma) 0x000000 - rsvd[2] [ 83.333165] xhci_hcd 0000:00:10.0: @ffff88005a16203c (virt) @5a16203c (dma) 0x000000 - rsvd[3] [ 83.333168] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.333170] xhci_hcd 0000:00:10.0: @ffff88005a162040 (virt) @5a162040 (dma) 0x000000 - ep_info [ 83.333172] xhci_hcd 0000:00:10.0: @ffff88005a162044 (virt) @5a162044 (dma) 0x400026 - ep_info2 [ 83.333175] xhci_hcd 0000:00:10.0: @ffff88005a162048 (virt) @5a162048 (dma) 0x5bf64401 - deq [ 83.333178] xhci_hcd 0000:00:10.0: @ffff88005a162050 (virt) @5a162050 (dma) 0x000000 - tx_info [ 83.333180] xhci_hcd 0000:00:10.0: @ffff88005a162054 (virt) @5a162054 (dma) 0x000000 - rsvd[0] [ 83.333183] xhci_hcd 0000:00:10.0: @ffff88005a162058 (virt) @5a162058 (dma) 0x000000 - rsvd[1] [ 83.333186] xhci_hcd 0000:00:10.0: @ffff88005a16205c (virt) @5a16205c (dma) 0x000000 - rsvd[2] [ 83.333188] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 83.333190] xhci_hcd 0000:00:10.0: @ffff88005a162060 (virt) @5a162060 (dma) 0x000000 - ep_info [ 83.333193] xhci_hcd 0000:00:10.0: @ffff88005a162064 (virt) @5a162064 (dma) 0x000000 - ep_info2 [ 83.333196] xhci_hcd 0000:00:10.0: @ffff88005a162068 (virt) @5a162068 (dma) 0x000000 - deq [ 83.333198] xhci_hcd 0000:00:10.0: @ffff88005a162070 (virt) @5a162070 (dma) 0x000000 - tx_info [ 83.333201] xhci_hcd 0000:00:10.0: @ffff88005a162074 (virt) @5a162074 (dma) 0x000000 - rsvd[0] [ 83.333204] xhci_hcd 0000:00:10.0: @ffff88005a162078 (virt) @5a162078 (dma) 0x000000 - rsvd[1] [ 83.333207] xhci_hcd 0000:00:10.0: @ffff88005a16207c (virt) @5a16207c (dma) 0x000000 - rsvd[2] [ 83.333209] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 83.333211] xhci_hcd 0000:00:10.0: @ffff88005a162080 (virt) @5a162080 (dma) 0x0b0000 - ep_info [ 83.333214] xhci_hcd 0000:00:10.0: @ffff88005a162084 (virt) @5a162084 (dma) 0x01003e - ep_info2 [ 83.333217] xhci_hcd 0000:00:10.0: @ffff88005a162088 (virt) @5a162088 (dma) 0x5bf64801 - deq [ 83.333219] xhci_hcd 0000:00:10.0: @ffff88005a162090 (virt) @5a162090 (dma) 0x010001 - tx_info [ 83.333222] xhci_hcd 0000:00:10.0: @ffff88005a162094 (virt) @5a162094 (dma) 0x000000 - rsvd[0] [ 83.333225] xhci_hcd 0000:00:10.0: @ffff88005a162098 (virt) @5a162098 (dma) 0x000000 - rsvd[1] [ 83.333227] xhci_hcd 0000:00:10.0: @ffff88005a16209c (virt) @5a16209c (dma) 0x000000 - rsvd[2] [ 83.333231] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.333233] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c0d0 (DMA) [ 83.333235] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.333274] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.333494] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.333498] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.333501] xhci_hcd 0000:00:10.0: @5d22c650 5d22c0c0 00000000 01000000 02008401 [ 83.333503] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.333506] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.333508] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.333510] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.333513] xhci_hcd 0000:00:10.0: Completed config ep cmd [ 83.333521] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c0d0 (DMA) [ 83.333523] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.333528] usb 6-3: Successful Endpoint Configure command [ 83.333532] xhci_hcd 0000:00:10.0: Output context after successful config ep cmd: [ 83.333534] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c660 (DMA) [ 83.333536] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.333540] xhci_hcd 0000:00:10.0: Slot Context: [ 83.333542] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c668, 4'hf); [ 83.333546] xhci_hcd 0000:00:10.0: @ffff88005a161000 (virt) @5a161000 (dma) 0x18300000 - dev_info [ 83.333549] xhci_hcd 0000:00:10.0: @ffff88005a161004 (virt) @5a161004 (dma) 0x030000 - dev_info2 [ 83.333552] xhci_hcd 0000:00:10.0: @ffff88005a161008 (virt) @5a161008 (dma) 0x000000 - tt_info [ 83.333555] xhci_hcd 0000:00:10.0: @ffff88005a16100c (virt) @5a16100c (dma) 0x18000002 - dev_state [ 83.333559] xhci_hcd 0000:00:10.0: @ffff88005a161010 (virt) @5a161010 (dma) 0x000000 - rsvd[0] [ 83.333562] xhci_hcd 0000:00:10.0: @ffff88005a161014 (virt) @5a161014 (dma) 0x000000 - rsvd[1] [ 83.333565] xhci_hcd 0000:00:10.0: @ffff88005a161018 (virt) @5a161018 (dma) 0x000000 - rsvd[2] [ 83.333567] xhci_hcd 0000:00:10.0: @ffff88005a16101c (virt) @5a16101c (dma) 0x000000 - rsvd[3] [ 83.333570] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.333572] xhci_hcd 0000:00:10.0: @ffff88005a161020 (virt) @5a161020 (dma) 0x000001 - ep_info [ 83.333575] xhci_hcd 0000:00:10.0: @ffff88005a161024 (virt) @5a161024 (dma) 0x400026 - ep_info2 [ 83.333578] xhci_hcd 0000:00:10.0: @ffff88005a161028 (virt) @5a161028 (dma) 0x5bf64401 - deq [ 83.333580] xhci_hcd 0000:00:10.0: @ffff88005a161030 (virt) @5a161030 (dma) 0x000000 - tx_info [ 83.333583] xhci_hcd 0000:00:10.0: @ffff88005a161034 (virt) @5a161034 (dma) 0x000000 - rsvd[0] [ 83.333586] xhci_hcd 0000:00:10.0: @ffff88005a161038 (virt) @5a161038 (dma) 0x000000 - rsvd[1] [ 83.333589] xhci_hcd 0000:00:10.0: @ffff88005a16103c (virt) @5a16103c (dma) 0x000000 - rsvd[2] [ 83.333591] xhci_hcd 0000:00:10.0: Endpoint 01 Context: [ 83.333593] xhci_hcd 0000:00:10.0: @ffff88005a161040 (virt) @5a161040 (dma) 0x000000 - ep_info [ 83.333596] xhci_hcd 0000:00:10.0: @ffff88005a161044 (virt) @5a161044 (dma) 0x000000 - ep_info2 [ 83.333599] xhci_hcd 0000:00:10.0: @ffff88005a161048 (virt) @5a161048 (dma) 0x000000 - deq [ 83.333602] xhci_hcd 0000:00:10.0: @ffff88005a161050 (virt) @5a161050 (dma) 0x000000 - tx_info [ 83.333604] xhci_hcd 0000:00:10.0: @ffff88005a161054 (virt) @5a161054 (dma) 0x000000 - rsvd[0] [ 83.333607] xhci_hcd 0000:00:10.0: @ffff88005a161058 (virt) @5a161058 (dma) 0x000000 - rsvd[1] [ 83.333610] xhci_hcd 0000:00:10.0: @ffff88005a16105c (virt) @5a16105c (dma) 0x000000 - rsvd[2] [ 83.333612] xhci_hcd 0000:00:10.0: Endpoint 02 Context: [ 83.333615] xhci_hcd 0000:00:10.0: @ffff88005a161060 (virt) @5a161060 (dma) 0x0b0001 - ep_info [ 83.333617] xhci_hcd 0000:00:10.0: @ffff88005a161064 (virt) @5a161064 (dma) 0x01003e - ep_info2 [ 83.333620] xhci_hcd 0000:00:10.0: @ffff88005a161068 (virt) @5a161068 (dma) 0x5bf64801 - deq [ 83.333623] xhci_hcd 0000:00:10.0: @ffff88005a161070 (virt) @5a161070 (dma) 0x010001 - tx_info [ 83.333626] xhci_hcd 0000:00:10.0: @ffff88005a161074 (virt) @5a161074 (dma) 0x000000 - rsvd[0] [ 83.333628] xhci_hcd 0000:00:10.0: @ffff88005a161078 (virt) @5a161078 (dma) 0x000000 - rsvd[1] [ 83.333631] xhci_hcd 0000:00:10.0: @ffff88005a16107c (virt) @5a16107c (dma) 0x000000 - rsvd[2] [ 83.333641] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.333643] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.333646] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64530 (DMA) [ 83.333648] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64540 (DMA) [ 83.333652] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.333911] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.333915] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.333917] xhci_hcd 0000:00:10.0: @5d22c660 5bf64530 00000000 01000000 02018001 [ 83.333920] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.333922] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.333923] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.333925] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.333927] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.333931] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866224 [ 83.333933] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.333936] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64530 (DMA) [ 83.333937] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64540 (DMA) [ 83.333939] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c670 (DMA) [ 83.333943] xhci_hcd 0000:00:10.0: Giveback URB ffff88005bf50780, len = 0, status = 0 [ 83.333952] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.333954] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.333958] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c678, 4'hf); [ 83.333972] xhci_hcd 0000:00:10.0: Endpoint 0x81 not halted, refusing to reset. [ 83.333979] usb 6-3: adding 6-3:1.0 (config #1, interface 0) [ 83.334106] hub 6-3:1.0: usb_probe_interface [ 83.334108] hub 6-3:1.0: usb_probe_interface - got id [ 83.334112] hub 6-3:1.0: USB hub found [ 83.334119] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.334121] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.334124] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64550 (DMA) [ 83.334126] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64560 (DMA) [ 83.334128] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64570 (DMA) [ 83.334167] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.334401] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.334406] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.334409] xhci_hcd 0000:00:10.0: @5d22c670 5bf64550 00000000 0d000006 02018001 [ 83.334412] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.334414] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.334416] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.334418] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.334420] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.334427] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866256 [ 83.334429] xhci_hcd 0000:00:10.0: WARN: short transfer on control ep [ 83.334431] xhci_hcd 0000:00:10.0: Waiting for status stage event [ 83.334433] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c680 (DMA) [ 83.334435] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.334437] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.334441] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c688, 4'hf); [ 83.334485] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.334487] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.334489] xhci_hcd 0000:00:10.0: @5d22c680 5bf64560 00000000 01000000 02018001 [ 83.334491] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.334493] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.334495] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.334496] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.334498] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.334500] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866272 [ 83.334502] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.334504] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64550 (DMA) [ 83.334506] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64560 (DMA) [ 83.334508] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64570 (DMA) [ 83.334510] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c690 (DMA) [ 83.334513] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c780, len = 9, status = 0 [ 83.334521] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.334523] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.334527] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c698, 4'hf); [ 83.334536] hub 6-3:1.0: 4 ports detected [ 83.334539] hub 6-3:1.0: standalone hub [ 83.334540] hub 6-3:1.0: individual port power switching [ 83.334542] hub 6-3:1.0: individual port over-current protection [ 83.334544] hub 6-3:1.0: Single TT [ 83.334545] hub 6-3:1.0: TT requires at most 32 FS bit times (2664 ns) [ 83.334547] hub 6-3:1.0: Port indicators are supported [ 83.334549] hub 6-3:1.0: power on to power good time: 100ms [ 83.334555] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.334557] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.334560] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64580 (DMA) [ 83.334561] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64590 (DMA) [ 83.334563] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf645a0 (DMA) [ 83.334566] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.334920] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.334923] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.334926] xhci_hcd 0000:00:10.0: @5d22c690 5bf64590 00000000 01000000 02018001 [ 83.334928] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.334930] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.334932] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.334934] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.334936] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.334939] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866320 [ 83.334941] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.334944] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64580 (DMA) [ 83.334945] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64590 (DMA) [ 83.334947] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf645a0 (DMA) [ 83.334949] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c6a0 (DMA) [ 83.334952] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c780, len = 2, status = 0 [ 83.334961] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.334963] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.334967] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c6a8, 4'hf); [ 83.334984] xhci_hcd 0000:00:10.0: xHCI version 96 needs hub TT think time and number of ports [ 83.334987] xhci_hcd 0000:00:10.0: Set up configure endpoint for hub device. [ 83.334989] xhci_hcd 0000:00:10.0: Slot 2 Input Context: [ 83.334992] xhci_hcd 0000:00:10.0: @ffff88005a127000 (virt) @5a127000 (dma) 0x000000 - drop flags [ 83.334994] xhci_hcd 0000:00:10.0: @ffff88005a127004 (virt) @5a127004 (dma) 0x000001 - add flags [ 83.334997] xhci_hcd 0000:00:10.0: @ffff88005a127008 (virt) @5a127008 (dma) 0x000000 - rsvd2[0] [ 83.335000] xhci_hcd 0000:00:10.0: @ffff88005a12700c (virt) @5a12700c (dma) 0x000000 - rsvd2[1] [ 83.335003] xhci_hcd 0000:00:10.0: @ffff88005a127010 (virt) @5a127010 (dma) 0x000000 - rsvd2[2] [ 83.335005] xhci_hcd 0000:00:10.0: @ffff88005a127014 (virt) @5a127014 (dma) 0x000000 - rsvd2[3] [ 83.335008] xhci_hcd 0000:00:10.0: @ffff88005a127018 (virt) @5a127018 (dma) 0x000000 - rsvd2[4] [ 83.335011] xhci_hcd 0000:00:10.0: @ffff88005a12701c (virt) @5a12701c (dma) 0x000000 - rsvd2[5] [ 83.335013] xhci_hcd 0000:00:10.0: Slot Context: [ 83.335015] xhci_hcd 0000:00:10.0: @ffff88005a127020 (virt) @5a127020 (dma) 0x1c300000 - dev_info [ 83.335018] xhci_hcd 0000:00:10.0: @ffff88005a127024 (virt) @5a127024 (dma) 0x4030000 - dev_info2 [ 83.335021] xhci_hcd 0000:00:10.0: @ffff88005a127028 (virt) @5a127028 (dma) 0x030000 - tt_info [ 83.335023] xhci_hcd 0000:00:10.0: @ffff88005a12702c (virt) @5a12702c (dma) 0x000000 - dev_state [ 83.335026] xhci_hcd 0000:00:10.0: @ffff88005a127030 (virt) @5a127030 (dma) 0x000000 - rsvd[0] [ 83.335029] xhci_hcd 0000:00:10.0: @ffff88005a127034 (virt) @5a127034 (dma) 0x000000 - rsvd[1] [ 83.335031] xhci_hcd 0000:00:10.0: @ffff88005a127038 (virt) @5a127038 (dma) 0x000000 - rsvd[2] [ 83.335034] xhci_hcd 0000:00:10.0: @ffff88005a12703c (virt) @5a12703c (dma) 0x000000 - rsvd[3] [ 83.335037] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.335039] xhci_hcd 0000:00:10.0: @ffff88005a127040 (virt) @5a127040 (dma) 0x000000 - ep_info [ 83.335041] xhci_hcd 0000:00:10.0: @ffff88005a127044 (virt) @5a127044 (dma) 0x000000 - ep_info2 [ 83.335044] xhci_hcd 0000:00:10.0: @ffff88005a127048 (virt) @5a127048 (dma) 0x000000 - deq [ 83.335046] xhci_hcd 0000:00:10.0: @ffff88005a127050 (virt) @5a127050 (dma) 0x000000 - tx_info [ 83.335049] xhci_hcd 0000:00:10.0: @ffff88005a127054 (virt) @5a127054 (dma) 0x000000 - rsvd[0] [ 83.335052] xhci_hcd 0000:00:10.0: @ffff88005a127058 (virt) @5a127058 (dma) 0x000000 - rsvd[1] [ 83.335055] xhci_hcd 0000:00:10.0: @ffff88005a12705c (virt) @5a12705c (dma) 0x000000 - rsvd[2] [ 83.335057] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.335060] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c0e0 (DMA) [ 83.335062] xhci_hcd 0000:00:10.0: // Ding dong! [ 83.335101] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 83.335239] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.335242] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.335245] xhci_hcd 0000:00:10.0: @5d22c6a0 5d22c0d0 00000000 01000000 02008401 [ 83.335247] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.335250] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.335251] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.335253] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 83.335261] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c0e0 (DMA) [ 83.335263] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 83.335265] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c6b0 (DMA) [ 83.335267] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.335271] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c6b8, 4'hf); [ 83.335282] usb 6-3: Successful Endpoint Configure command [ 83.335284] xhci_hcd 0000:00:10.0: Slot 2 Output Context: [ 83.335286] xhci_hcd 0000:00:10.0: Slot Context: [ 83.335288] xhci_hcd 0000:00:10.0: @ffff88005a161000 (virt) @5a161000 (dma) 0x1c300000 - dev_info [ 83.335291] xhci_hcd 0000:00:10.0: @ffff88005a161004 (virt) @5a161004 (dma) 0x4030000 - dev_info2 [ 83.335294] xhci_hcd 0000:00:10.0: @ffff88005a161008 (virt) @5a161008 (dma) 0x030000 - tt_info [ 83.335296] xhci_hcd 0000:00:10.0: @ffff88005a16100c (virt) @5a16100c (dma) 0x18000002 - dev_state [ 83.335298] xhci_hcd 0000:00:10.0: @ffff88005a161010 (virt) @5a161010 (dma) 0x000000 - rsvd[0] [ 83.335301] xhci_hcd 0000:00:10.0: @ffff88005a161014 (virt) @5a161014 (dma) 0x000000 - rsvd[1] [ 83.335303] xhci_hcd 0000:00:10.0: @ffff88005a161018 (virt) @5a161018 (dma) 0x000000 - rsvd[2] [ 83.335306] xhci_hcd 0000:00:10.0: @ffff88005a16101c (virt) @5a16101c (dma) 0x000000 - rsvd[3] [ 83.335308] xhci_hcd 0000:00:10.0: Endpoint 00 Context: [ 83.335310] xhci_hcd 0000:00:10.0: @ffff88005a161020 (virt) @5a161020 (dma) 0x000001 - ep_info [ 83.335312] xhci_hcd 0000:00:10.0: @ffff88005a161024 (virt) @5a161024 (dma) 0x400026 - ep_info2 [ 83.335315] xhci_hcd 0000:00:10.0: @ffff88005a161028 (virt) @5a161028 (dma) 0x5bf64401 - deq [ 83.335317] xhci_hcd 0000:00:10.0: @ffff88005a161030 (virt) @5a161030 (dma) 0x000000 - tx_info [ 83.335320] xhci_hcd 0000:00:10.0: @ffff88005a161034 (virt) @5a161034 (dma) 0x000000 - rsvd[0] [ 83.335322] xhci_hcd 0000:00:10.0: @ffff88005a161038 (virt) @5a161038 (dma) 0x000000 - rsvd[1] [ 83.335324] xhci_hcd 0000:00:10.0: @ffff88005a16103c (virt) @5a16103c (dma) 0x000000 - rsvd[2] [ 83.335334] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.335336] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.335339] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf645b0 (DMA) [ 83.335341] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf645c0 (DMA) [ 83.335343] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf645d0 (DMA) [ 83.335346] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.335670] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.335673] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.335676] xhci_hcd 0000:00:10.0: @5d22c6b0 5bf645c0 00000000 01000000 02018001 [ 83.335678] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.335680] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.335682] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.335684] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.335686] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.335689] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866368 [ 83.335691] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.335694] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf645b0 (DMA) [ 83.335695] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf645c0 (DMA) [ 83.335697] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf645d0 (DMA) [ 83.335699] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c6c0 (DMA) [ 83.335702] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c780, len = 4, status = 0 [ 83.335711] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.335713] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.335717] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c6c8, 4'hf); [ 83.335729] hub 6-3:1.0: local power source is good [ 83.335732] hub 6-3:1.0: enabling power on all ports [ 83.335738] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.335740] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.335742] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf645e0 (DMA) [ 83.335744] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf645f0 (DMA) [ 83.335748] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.336044] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.336047] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.336050] xhci_hcd 0000:00:10.0: @5d22c6c0 5bf645e0 00000000 01000000 02018001 [ 83.336052] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.336055] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.336056] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.336058] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.336060] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.336064] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866400 [ 83.336066] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.336068] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf645e0 (DMA) [ 83.336070] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf645f0 (DMA) [ 83.336072] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c6d0 (DMA) [ 83.336075] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c6c0, len = 0, status = 0 [ 83.336084] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.336086] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.336090] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c6d8, 4'hf); [ 83.336106] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.336108] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.336111] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64600 (DMA) [ 83.336113] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64610 (DMA) [ 83.336116] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.336418] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.336421] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.336424] xhci_hcd 0000:00:10.0: @5d22c6d0 5bf64600 00000000 01000000 02018001 [ 83.336426] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.336428] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.336430] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.336432] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.336434] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.336438] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866432 [ 83.336440] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.336442] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64600 (DMA) [ 83.336444] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64610 (DMA) [ 83.336446] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c6e0 (DMA) [ 83.336449] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c6c0, len = 0, status = 0 [ 83.336457] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.336459] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.336464] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c6e8, 4'hf); [ 83.336479] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.336481] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.336484] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64620 (DMA) [ 83.336486] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64630 (DMA) [ 83.336489] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.336758] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.336761] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.336764] xhci_hcd 0000:00:10.0: @5d22c6e0 5bf64620 00000000 01000000 02018001 [ 83.336766] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.336769] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.336770] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.336772] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.336774] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.336778] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866464 [ 83.336780] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.336782] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64620 (DMA) [ 83.336784] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64630 (DMA) [ 83.336786] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c6f0 (DMA) [ 83.336789] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c6c0, len = 0, status = 0 [ 83.336797] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.336799] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.336803] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c6f8, 4'hf); [ 83.336819] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.336821] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.336824] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64640 (DMA) [ 83.336826] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64650 (DMA) [ 83.336829] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.337012] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.337015] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.337017] xhci_hcd 0000:00:10.0: @5d22c6f0 5bf64640 00000000 01000000 02018001 [ 83.337020] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.337022] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.337024] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.337026] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.337028] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.337031] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866496 [ 83.337033] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.337036] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64640 (DMA) [ 83.337038] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64650 (DMA) [ 83.337040] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c700 (DMA) [ 83.337043] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a75c6c0, len = 0, status = 0 [ 83.337051] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.337053] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.337057] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c708, 4'hf); [ 83.430094] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.430099] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.430102] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64660 (DMA) [ 83.430104] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64670 (DMA) [ 83.430106] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64680 (DMA) [ 83.430110] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.430538] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.430542] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.430545] xhci_hcd 0000:00:10.0: @5d22c700 5bf64670 00000000 01000000 02018001 [ 83.430547] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.430549] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.430551] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.430553] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.430555] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.430559] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866544 [ 83.430561] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.430563] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64660 (DMA) [ 83.430565] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64670 (DMA) [ 83.430567] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64680 (DMA) [ 83.430569] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c710 (DMA) [ 83.430572] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a666e40, len = 4, status = 0 [ 83.430581] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.430583] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.430587] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c718, 4'hf); [ 83.430604] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.430606] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.430609] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64690 (DMA) [ 83.430611] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf646a0 (DMA) [ 83.430612] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf646b0 (DMA) [ 83.430616] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.431040] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.431043] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.431046] xhci_hcd 0000:00:10.0: @5d22c710 5bf646a0 00000000 01000000 02018001 [ 83.431048] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.431050] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.431052] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.431054] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.431056] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.431059] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866592 [ 83.431061] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.431064] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64690 (DMA) [ 83.431066] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf646a0 (DMA) [ 83.431067] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf646b0 (DMA) [ 83.431069] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c720 (DMA) [ 83.431073] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a666e40, len = 4, status = 0 [ 83.431081] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.431083] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.431087] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c728, 4'hf); [ 83.431104] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.431107] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.431109] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf646c0 (DMA) [ 83.431111] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf646d0 (DMA) [ 83.431113] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf646e0 (DMA) [ 83.431116] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.431540] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.431543] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.431546] xhci_hcd 0000:00:10.0: @5d22c720 5bf646d0 00000000 01000000 02018001 [ 83.431548] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.431550] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.431552] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.431554] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.431556] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.431559] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866640 [ 83.431561] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.431564] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf646c0 (DMA) [ 83.431565] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf646d0 (DMA) [ 83.431567] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf646e0 (DMA) [ 83.431569] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c730 (DMA) [ 83.431572] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a666e40, len = 4, status = 0 [ 83.431581] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.431583] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.431587] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c738, 4'hf); [ 83.431604] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 83.431606] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.431609] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf646f0 (DMA) [ 83.431610] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64700 (DMA) [ 83.431612] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64710 (DMA) [ 83.431616] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 83.432038] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 83.432042] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 83.432044] xhci_hcd 0000:00:10.0: @5d22c730 5bf64700 00000000 01000000 02018001 [ 83.432047] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 83.432049] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.432050] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 83.432052] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 83.432054] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 83.432058] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866688 [ 83.432060] xhci_hcd 0000:00:10.0: Successful control transfer! [ 83.432063] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf646f0 (DMA) [ 83.432064] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64700 (DMA) [ 83.432066] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64710 (DMA) [ 83.432068] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c740 (DMA) [ 83.432071] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a666e40, len = 4, status = 0 [ 83.432080] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 83.432082] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 83.432086] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c748, 4'hf); [ 83.432103] xhci_hcd 0000:00:10.0: ep 0x81 - urb len = 0x1 (1), addr = 0x5bc0d668, num_trbs = 1 [ 83.432106] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 83.432109] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64810 (DMA) [ 83.432112] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h3, 4'hf); [ 83.432145] hub 6-3:1.0: state 7 ports 4 chg 0000 evt 0000 [ 86.020136] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 86.020141] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c0f0 (DMA) [ 86.020144] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 86.020146] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c100 (DMA) [ 86.020148] xhci_hcd 0000:00:10.0: // Ding dong! [ 86.020151] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 86.020249] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 86.020252] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 86.020255] xhci_hcd 0000:00:10.0: @5d22c740 5d22c0e0 00000000 01000000 01008401 [ 86.020258] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 86.020260] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.020262] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 86.020264] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 86.020268] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c0f0 (DMA) [ 86.020270] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 86.020272] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c750 (DMA) [ 86.020274] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.020278] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c758, 4'hf); [ 86.021767] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 86.021771] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 86.021773] xhci_hcd 0000:00:10.0: @5d22c750 5d22c0f0 00000000 13000000 01008401 [ 86.021776] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 86.021778] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.021780] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 86.021782] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 86.021792] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c100 (DMA) [ 86.021794] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 86.021796] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c760 (DMA) [ 86.021798] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.021803] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c768, 4'hf); [ 86.021814] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918420, 32'h11261, 4'hf); [ 86.040159] usb 6-1: usb auto-suspend [ 86.050152] hub 6-3:1.0: hub_suspend [ 86.050200] xhci_hcd 0000:00:10.0: Cancel URB ffff88005a75c780 [ 86.050202] xhci_hcd 0000:00:10.0: Event ring: [ 86.050205] xhci_hcd 0000:00:10.0: @5d22c400 01000000 00000000 01000000 00008801 [ 86.050208] xhci_hcd 0000:00:10.0: @5d22c410 03000000 00000000 01000000 00008801 [ 86.050210] xhci_hcd 0000:00:10.0: @5d22c420 5d22c000 00000000 01000000 01008401 [ 86.050213] xhci_hcd 0000:00:10.0: @5d22c430 5d22c010 00000000 01000000 01008401 [ 86.050215] xhci_hcd 0000:00:10.0: @5d22c440 5d22c820 00000000 01000000 01018001 [ 86.050217] xhci_hcd 0000:00:10.0: @5d22c450 5d22c850 00000000 01000000 01018001 [ 86.050219] xhci_hcd 0000:00:10.0: @5d22c460 5d22c880 00000000 01000000 01018001 [ 86.050222] xhci_hcd 0000:00:10.0: @5d22c470 5d22c8b0 00000000 01000000 01018001 [ 86.050224] xhci_hcd 0000:00:10.0: @5d22c480 5d22c8d0 00000000 0d0000fb 01018001 [ 86.050226] xhci_hcd 0000:00:10.0: @5d22c490 5d22c8e0 00000000 01000000 01018001 [ 86.050229] xhci_hcd 0000:00:10.0: @5d22c4a0 5d22c900 00000000 0d0000d9 01018001 [ 86.050231] xhci_hcd 0000:00:10.0: @5d22c4b0 5d22c910 00000000 01000000 01018001 [ 86.050233] xhci_hcd 0000:00:10.0: @5d22c4c0 5d22c930 00000000 0d0000e1 01018001 [ 86.050235] xhci_hcd 0000:00:10.0: @5d22c4d0 5d22c940 00000000 01000000 01018001 [ 86.050238] xhci_hcd 0000:00:10.0: @5d22c4e0 5d22c020 00000000 01000000 01008401 [ 86.050240] xhci_hcd 0000:00:10.0: @5d22c4f0 5d22c960 00000000 01000000 01018001 [ 86.050242] xhci_hcd 0000:00:10.0: @5d22c500 5d22c980 00000000 0600000f 01018001 [ 86.050244] xhci_hcd 0000:00:10.0: @5d22c510 5d22c030 00000000 01000000 01008401 [ 86.050247] xhci_hcd 0000:00:10.0: @5d22c520 5d22c040 00000000 01000000 01008401 [ 86.050249] xhci_hcd 0000:00:10.0: @5d22c530 5d22c9b0 00000000 0600000f 01018001 [ 86.050251] xhci_hcd 0000:00:10.0: @5d22c540 5d22c050 00000000 01000000 01008401 [ 86.050254] xhci_hcd 0000:00:10.0: @5d22c550 5d22c060 00000000 01000000 01008401 [ 86.050256] xhci_hcd 0000:00:10.0: @5d22c560 5d22c9e0 00000000 0600000f 01018001 [ 86.050258] xhci_hcd 0000:00:10.0: @5d22c570 5d22c070 00000000 01000000 01008401 [ 86.050260] xhci_hcd 0000:00:10.0: @5d22c580 5d22c080 00000000 01000000 01008401 [ 86.050263] xhci_hcd 0000:00:10.0: @5d22c590 5d22c090 00000000 01000000 02008401 [ 86.050265] xhci_hcd 0000:00:10.0: @5d22c5a0 03000000 00000000 01000000 00008801 [ 86.050267] xhci_hcd 0000:00:10.0: @5d22c5b0 5d22c0a0 00000000 13000000 02008401 [ 86.050269] xhci_hcd 0000:00:10.0: @5d22c5c0 5d22c0b0 00000000 01000000 02008401 [ 86.050272] xhci_hcd 0000:00:10.0: @5d22c5d0 5bf64420 00000000 01000000 02018001 [ 86.050274] xhci_hcd 0000:00:10.0: @5d22c5e0 5bf64450 00000000 01000000 02018001 [ 86.050276] xhci_hcd 0000:00:10.0: @5d22c5f0 5bf64480 00000000 01000000 02018001 [ 86.050279] xhci_hcd 0000:00:10.0: @5d22c600 5bf644b0 00000000 01000000 02018001 [ 86.050281] xhci_hcd 0000:00:10.0: @5d22c610 5bf644d0 00000000 0d0000fb 02018001 [ 86.050283] xhci_hcd 0000:00:10.0: @5d22c620 5bf644e0 00000000 01000000 02018001 [ 86.050285] xhci_hcd 0000:00:10.0: @5d22c630 5bf64500 00000000 0d0000e9 02018001 [ 86.050288] xhci_hcd 0000:00:10.0: @5d22c640 5bf64510 00000000 01000000 02018001 [ 86.050290] xhci_hcd 0000:00:10.0: @5d22c650 5d22c0c0 00000000 01000000 02008401 [ 86.050292] xhci_hcd 0000:00:10.0: @5d22c660 5bf64530 00000000 01000000 02018001 [ 86.050294] xhci_hcd 0000:00:10.0: @5d22c670 5bf64550 00000000 0d000006 02018001 [ 86.050297] xhci_hcd 0000:00:10.0: @5d22c680 5bf64560 00000000 01000000 02018001 [ 86.050299] xhci_hcd 0000:00:10.0: @5d22c690 5bf64590 00000000 01000000 02018001 [ 86.050301] xhci_hcd 0000:00:10.0: @5d22c6a0 5d22c0d0 00000000 01000000 02008401 [ 86.050304] xhci_hcd 0000:00:10.0: @5d22c6b0 5bf645c0 00000000 01000000 02018001 [ 86.050306] xhci_hcd 0000:00:10.0: @5d22c6c0 5bf645e0 00000000 01000000 02018001 [ 86.050308] xhci_hcd 0000:00:10.0: @5d22c6d0 5bf64600 00000000 01000000 02018001 [ 86.050310] xhci_hcd 0000:00:10.0: @5d22c6e0 5bf64620 00000000 01000000 02018001 [ 86.050313] xhci_hcd 0000:00:10.0: @5d22c6f0 5bf64640 00000000 01000000 02018001 [ 86.050315] xhci_hcd 0000:00:10.0: @5d22c700 5bf64670 00000000 01000000 02018001 [ 86.050317] xhci_hcd 0000:00:10.0: @5d22c710 5bf646a0 00000000 01000000 02018001 [ 86.050319] xhci_hcd 0000:00:10.0: @5d22c720 5bf646d0 00000000 01000000 02018001 [ 86.050322] xhci_hcd 0000:00:10.0: @5d22c730 5bf64700 00000000 01000000 02018001 [ 86.050324] xhci_hcd 0000:00:10.0: @5d22c740 5d22c0e0 00000000 01000000 01008401 [ 86.050326] xhci_hcd 0000:00:10.0: @5d22c750 5d22c0f0 00000000 13000000 01008401 [ 86.050328] xhci_hcd 0000:00:10.0: @5d22c760 00000000 00000000 00000000 00000000 [ 86.050331] xhci_hcd 0000:00:10.0: @5d22c770 00000000 00000000 00000000 00000000 [ 86.050333] xhci_hcd 0000:00:10.0: @5d22c780 00000000 00000000 00000000 00000000 [ 86.050335] xhci_hcd 0000:00:10.0: @5d22c790 00000000 00000000 00000000 00000000 [ 86.050337] xhci_hcd 0000:00:10.0: @5d22c7a0 00000000 00000000 00000000 00000000 [ 86.050339] xhci_hcd 0000:00:10.0: @5d22c7b0 00000000 00000000 00000000 00000000 [ 86.050342] xhci_hcd 0000:00:10.0: @5d22c7c0 00000000 00000000 00000000 00000000 [ 86.050344] xhci_hcd 0000:00:10.0: @5d22c7d0 00000000 00000000 00000000 00000000 [ 86.050346] xhci_hcd 0000:00:10.0: @5d22c7e0 00000000 00000000 00000000 00000000 [ 86.050348] xhci_hcd 0000:00:10.0: @5d22c7f0 00000000 00000000 00000000 00000000 [ 86.050350] xhci_hcd 0000:00:10.0: Endpoint ring: [ 86.050353] xhci_hcd 0000:00:10.0: @5bf64800 5bc0d668 00000000 00000001 00000425 [ 86.050355] xhci_hcd 0000:00:10.0: @5bf64810 00000000 00000000 00000000 00000000 [ 86.050357] xhci_hcd 0000:00:10.0: @5bf64820 00000000 00000000 00000000 00000000 [ 86.050359] xhci_hcd 0000:00:10.0: @5bf64830 00000000 00000000 00000000 00000000 [ 86.050361] xhci_hcd 0000:00:10.0: @5bf64840 00000000 00000000 00000000 00000000 [ 86.050364] xhci_hcd 0000:00:10.0: @5bf64850 00000000 00000000 00000000 00000000 [ 86.050366] xhci_hcd 0000:00:10.0: @5bf64860 00000000 00000000 00000000 00000000 [ 86.050368] xhci_hcd 0000:00:10.0: @5bf64870 00000000 00000000 00000000 00000000 [ 86.050370] xhci_hcd 0000:00:10.0: @5bf64880 00000000 00000000 00000000 00000000 [ 86.050372] xhci_hcd 0000:00:10.0: @5bf64890 00000000 00000000 00000000 00000000 [ 86.050375] xhci_hcd 0000:00:10.0: @5bf648a0 00000000 00000000 00000000 00000000 [ 86.050377] xhci_hcd 0000:00:10.0: @5bf648b0 00000000 00000000 00000000 00000000 [ 86.050379] xhci_hcd 0000:00:10.0: @5bf648c0 00000000 00000000 00000000 00000000 [ 86.050381] xhci_hcd 0000:00:10.0: @5bf648d0 00000000 00000000 00000000 00000000 [ 86.050383] xhci_hcd 0000:00:10.0: @5bf648e0 00000000 00000000 00000000 00000000 [ 86.050385] xhci_hcd 0000:00:10.0: @5bf648f0 00000000 00000000 00000000 00000000 [ 86.050388] xhci_hcd 0000:00:10.0: @5bf64900 00000000 00000000 00000000 00000000 [ 86.050390] xhci_hcd 0000:00:10.0: @5bf64910 00000000 00000000 00000000 00000000 [ 86.050392] xhci_hcd 0000:00:10.0: @5bf64920 00000000 00000000 00000000 00000000 [ 86.050394] xhci_hcd 0000:00:10.0: @5bf64930 00000000 00000000 00000000 00000000 [ 86.050396] xhci_hcd 0000:00:10.0: @5bf64940 00000000 00000000 00000000 00000000 [ 86.050399] xhci_hcd 0000:00:10.0: @5bf64950 00000000 00000000 00000000 00000000 [ 86.050401] xhci_hcd 0000:00:10.0: @5bf64960 00000000 00000000 00000000 00000000 [ 86.050403] xhci_hcd 0000:00:10.0: @5bf64970 00000000 00000000 00000000 00000000 [ 86.050405] xhci_hcd 0000:00:10.0: @5bf64980 00000000 00000000 00000000 00000000 [ 86.050407] xhci_hcd 0000:00:10.0: @5bf64990 00000000 00000000 00000000 00000000 [ 86.050410] xhci_hcd 0000:00:10.0: @5bf649a0 00000000 00000000 00000000 00000000 [ 86.050412] xhci_hcd 0000:00:10.0: @5bf649b0 00000000 00000000 00000000 00000000 [ 86.050414] xhci_hcd 0000:00:10.0: @5bf649c0 00000000 00000000 00000000 00000000 [ 86.050416] xhci_hcd 0000:00:10.0: @5bf649d0 00000000 00000000 00000000 00000000 [ 86.050418] xhci_hcd 0000:00:10.0: @5bf649e0 00000000 00000000 00000000 00000000 [ 86.050421] xhci_hcd 0000:00:10.0: @5bf649f0 00000000 00000000 00000000 00000000 [ 86.050423] xhci_hcd 0000:00:10.0: @5bf64a00 00000000 00000000 00000000 00000000 [ 86.050425] xhci_hcd 0000:00:10.0: @5bf64a10 00000000 00000000 00000000 00000000 [ 86.050427] xhci_hcd 0000:00:10.0: @5bf64a20 00000000 00000000 00000000 00000000 [ 86.050429] xhci_hcd 0000:00:10.0: @5bf64a30 00000000 00000000 00000000 00000000 [ 86.050431] xhci_hcd 0000:00:10.0: @5bf64a40 00000000 00000000 00000000 00000000 [ 86.050434] xhci_hcd 0000:00:10.0: @5bf64a50 00000000 00000000 00000000 00000000 [ 86.050436] xhci_hcd 0000:00:10.0: @5bf64a60 00000000 00000000 00000000 00000000 [ 86.050438] xhci_hcd 0000:00:10.0: @5bf64a70 00000000 00000000 00000000 00000000 [ 86.050440] xhci_hcd 0000:00:10.0: @5bf64a80 00000000 00000000 00000000 00000000 [ 86.050442] xhci_hcd 0000:00:10.0: @5bf64a90 00000000 00000000 00000000 00000000 [ 86.050445] xhci_hcd 0000:00:10.0: @5bf64aa0 00000000 00000000 00000000 00000000 [ 86.050447] xhci_hcd 0000:00:10.0: @5bf64ab0 00000000 00000000 00000000 00000000 [ 86.050449] xhci_hcd 0000:00:10.0: @5bf64ac0 00000000 00000000 00000000 00000000 [ 86.050451] xhci_hcd 0000:00:10.0: @5bf64ad0 00000000 00000000 00000000 00000000 [ 86.050453] xhci_hcd 0000:00:10.0: @5bf64ae0 00000000 00000000 00000000 00000000 [ 86.050455] xhci_hcd 0000:00:10.0: @5bf64af0 00000000 00000000 00000000 00000000 [ 86.050458] xhci_hcd 0000:00:10.0: @5bf64b00 00000000 00000000 00000000 00000000 [ 86.050460] xhci_hcd 0000:00:10.0: @5bf64b10 00000000 00000000 00000000 00000000 [ 86.050462] xhci_hcd 0000:00:10.0: @5bf64b20 00000000 00000000 00000000 00000000 [ 86.050464] xhci_hcd 0000:00:10.0: @5bf64b30 00000000 00000000 00000000 00000000 [ 86.050466] xhci_hcd 0000:00:10.0: @5bf64b40 00000000 00000000 00000000 00000000 [ 86.050469] xhci_hcd 0000:00:10.0: @5bf64b50 00000000 00000000 00000000 00000000 [ 86.050471] xhci_hcd 0000:00:10.0: @5bf64b60 00000000 00000000 00000000 00000000 [ 86.050473] xhci_hcd 0000:00:10.0: @5bf64b70 00000000 00000000 00000000 00000000 [ 86.050475] xhci_hcd 0000:00:10.0: @5bf64b80 00000000 00000000 00000000 00000000 [ 86.050477] xhci_hcd 0000:00:10.0: @5bf64b90 00000000 00000000 00000000 00000000 [ 86.050480] xhci_hcd 0000:00:10.0: @5bf64ba0 00000000 00000000 00000000 00000000 [ 86.050482] xhci_hcd 0000:00:10.0: @5bf64bb0 00000000 00000000 00000000 00000000 [ 86.050484] xhci_hcd 0000:00:10.0: @5bf64bc0 00000000 00000000 00000000 00000000 [ 86.050486] xhci_hcd 0000:00:10.0: @5bf64bd0 00000000 00000000 00000000 00000000 [ 86.050488] xhci_hcd 0000:00:10.0: @5bf64be0 00000000 00000000 00000000 00000000 [ 86.050490] xhci_hcd 0000:00:10.0: @5bf64bf0 5bf64800 00000000 00000000 00001802 [ 86.050494] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 86.050497] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c110 (DMA) [ 86.050498] xhci_hcd 0000:00:10.0: // Ding dong! [ 86.050502] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 86.050626] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 86.050630] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 86.050632] xhci_hcd 0000:00:10.0: @5d22c760 5d22c100 00000000 01000000 02008401 [ 86.050635] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 86.050637] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.050639] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 86.050641] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 86.050644] xhci_hcd 0000:00:10.0: Cancelling TD starting at ffff88005bf64800, 0x5bf64800 (dma). [ 86.050647] xhci_hcd 0000:00:10.0: Cancel TRB ffff88005bf64800 (0x5bf64800 dma) in seg ffff88005badce00 (0x5bf64800 dma) [ 86.050650] xhci_hcd 0000:00:10.0: Giveback cancelled URB ffff88005a75c780 [ 86.050665] xhci_hcd 0000:00:10.0: cancelled URB given back [ 86.050667] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c110 (DMA) [ 86.050669] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 86.050671] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c770 (DMA) [ 86.050673] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.050677] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c778, 4'hf); [ 86.050690] xhci_hcd 0000:00:10.0: Queueing ctrl tx for slot id 2, ep 0 [ 86.050694] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 86.050697] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64720 (DMA) [ 86.050699] xhci_hcd 0000:00:10.0: Ring enq = 0x5bf64730 (DMA) [ 86.050702] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918808, 32'h1, 4'hf); [ 86.051018] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 86.051021] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 86.051024] xhci_hcd 0000:00:10.0: @5d22c770 5bf64720 00000000 01000000 02018001 [ 86.051026] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 86.051028] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.051030] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 86.051032] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_tx_event [ 86.051034] xhci_hcd 0000:00:10.0: handle_tx_event - ep index = 0 [ 86.051038] xhci_hcd 0000:00:10.0: DMA address or buffer contents= 1542866720 [ 86.051040] xhci_hcd 0000:00:10.0: Successful control transfer! [ 86.051043] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64720 (DMA) [ 86.051044] xhci_hcd 0000:00:10.0: Ring deq = 0x5bf64730 (DMA) [ 86.051046] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c780 (DMA) [ 86.051050] xhci_hcd 0000:00:10.0: Giveback URB ffff88005a7573c0, len = 0, status = 0 [ 86.051063] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_tx_event [ 86.051065] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.051070] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c788, 4'hf); [ 86.051088] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 86.051093] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c120 (DMA) [ 86.051095] xhci_hcd 0000:00:10.0: Endpoint state = 0x1 [ 86.051097] xhci_hcd 0000:00:10.0: Command ring enq = 0x5d22c130 (DMA) [ 86.051098] xhci_hcd 0000:00:10.0: // Ding dong! [ 86.051102] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918800, 32'h0, 4'hf); [ 86.052765] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 86.052768] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 86.052771] xhci_hcd 0000:00:10.0: @5d22c780 5d22c110 00000000 13000000 02008401 [ 86.052773] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 86.052775] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.052777] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 86.052779] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 86.052782] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c120 (DMA) [ 86.052784] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 86.052786] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c790 (DMA) [ 86.052788] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.052792] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c798, 4'hf); [ 86.052874] xhci_hcd 0000:00:10.0: op reg status = 00000008 [ 86.052877] xhci_hcd 0000:00:10.0: Event ring dequeue ptr: [ 86.052880] xhci_hcd 0000:00:10.0: @5d22c790 5d22c120 00000000 01000000 02008401 [ 86.052882] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918024, 32'h8, 4'hf); [ 86.052884] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.052886] xhci_hcd 0000:00:10.0: xhci_handle_event - OS owns TRB [ 86.052888] xhci_hcd 0000:00:10.0: xhci_handle_event - calling handle_cmd_completion [ 86.052902] xhci_hcd 0000:00:10.0: Command ring deq = 0x5d22c130 (DMA) [ 86.052904] xhci_hcd 0000:00:10.0: xhci_handle_event - returned from handle_cmd_completion [ 86.052906] xhci_hcd 0000:00:10.0: Event ring deq = 0x5d22c7a0 (DMA) [ 86.052907] xhci_hcd 0000:00:10.0: In xhci_handle_event [ 86.052912] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 64'hffffc90001918638, 64'h5d22c7a8, 4'hf); [ 86.052919] xhci_hcd 0000:00:10.0: `MEM_WRITE_DWORD(3'b000, 32'hffffc90001918440, 32'h10e61, 4'hf); [ 86.070132] usb 6-3: usb auto-suspend
