On Tue, Nov 09, 2010 at 12:40:17PM +0100, Matthieu CASTET wrote: Hi Matthieu, > Pavankumar Kondeti a écrit : >> This patch adds the basic support for the USB Device Controller on Qualcomm >> MSM family of SOCs. The controller supports upto 16 endpoints including the >> default endpoint (ep0). All the data transfers are driven by DMA. >> >> VBUS line is also connected to PMIC chip. The module controlling PMIC chip >> notifies about cable connect/disconnect events. Hence, PHY comparators >> are turned off in low power mode. >> >> This driver was originally developed by Google and is available at >> http://android.git.kernel.org/?p=kernel/experimental.git. >> >> + >> +#define USB_ID (MSM_USB_BASE + 0x0000) >> +#define USB_HWGENERAL (MSM_USB_BASE + 0x0004) >> +#define USB_HWHOST (MSM_USB_BASE + 0x0008) >> +#define USB_HWDEVICE (MSM_USB_BASE + 0x000C) >> +#define USB_HWTXBUF (MSM_USB_BASE + 0x0010) >> +#define USB_HWRXBUF (MSM_USB_BASE + 0x0014) >> + >> +#ifdef CONFIG_ARCH_MSM7X00A >> +#define USB_SBUSCFG (MSM_USB_BASE + 0x0090) >> +#else >> +#define USB_AHBBURST (MSM_USB_BASE + 0x0090) >> +#define USB_AHBMODE (MSM_USB_BASE + 0x0098) >> +#endif >> + >> +#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */ >> +#define USB_HCIVERSION (MSM_USB_BASE + 0x0102) /* 16 bit */ >> +#define USB_HCSPARAMS (MSM_USB_BASE + 0x0104) >> +#define USB_HCCPARAMS (MSM_USB_BASE + 0x0108) >> +#define USB_DCIVERSION (MSM_USB_BASE + 0x0120) /* 16 bit */ >> +#define USB_USBCMD (MSM_USB_BASE + 0x0140) >> +#define USB_USBSTS (MSM_USB_BASE + 0x0144) >> +#define USB_USBINTR (MSM_USB_BASE + 0x0148) >> +#define USB_FRINDEX (MSM_USB_BASE + 0x014C) >> +#define USB_DEVICEADDR (MSM_USB_BASE + 0x0154) >> +#define USB_ENDPOINTLISTADDR (MSM_USB_BASE + 0x0158) >> +#define USB_BURSTSIZE (MSM_USB_BASE + 0x0160) >> +#define USB_TXFILLTUNING (MSM_USB_BASE + 0x0164) >> +#define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170) >> +#define USB_ENDPTNAK (MSM_USB_BASE + 0x0178) >> +#define USB_ENDPTNAKEN (MSM_USB_BASE + 0x017C) >> +#define USB_PORTSC (MSM_USB_BASE + 0x0184) >> +#define USB_OTGSC (MSM_USB_BASE + 0x01A4) >> +#define USB_USBMODE (MSM_USB_BASE + 0x01A8) >> +#define USB_ENDPTSETUPSTAT (MSM_USB_BASE + 0x01AC) >> +#define USB_ENDPTPRIME (MSM_USB_BASE + 0x01B0) >> +#define USB_ENDPTFLUSH (MSM_USB_BASE + 0x01B4) >> +#define USB_ENDPTSTAT (MSM_USB_BASE + 0x01B8) >> +#define USB_ENDPTCOMPLETE (MSM_USB_BASE + 0x01BC) >> +#define USB_ENDPTCTRL(n) (MSM_USB_BASE + 0x01C0 + (4 * (n))) >> + >> + >> +#define USBCMD_RESET 2 >> +#define USBCMD_ATTACH 1 >> +#define USBCMD_ATDTW (1 << 14) >> + >> +#define USBMODE_DEVICE 2 >> +#define USBMODE_HOST 3 >> + >> > This look like the arc/chipidea/mips ehci otg core. Yes. It is chipidea core for ARM. > > Why can't you reuse the ci13xxx_udc.c driver ? > Or if ci13xxx_udc.c is too bad, rewrite a new generic version for this core. > ci13xxx_udc.c driver registers with PCI subsytem (ours is a platform subsystem), does not manage clocks. msm72k_udc.c also takes care of initializing the integrated PHY. We also need to program special registers (MSM-ARM specific) upon resetting the hardware. Thanks, Pavan -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
