On Thu, 6 May 2010, Anton Vorontsov wrote: > It appears that the 'pehcd' driver checks the X bit only if the > transaction is halted, otherwise the error is so far > insignificant. > > I didn't find where exactly ISP1760 spec mandates 'H && X' > handling (maybe it's in the EHCI spec?), Yes, it is described implicitly in the EHCI spec, section 4.10.3. Transaction errors cause the status field to be updated to reflect the type of error, but the transaction continues to be retried until the Active bit is set to 0. When the error counter reaches 0, the Halt bit is set and the Active bit is cleared. Alan Stern -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
