The Endpoint Context Field at Offset 0x08 is defined as follows:
- Bit 0: Dequeue Cycle State (DCS)
- Bits 3:1: RsvdZ (Reserved and Zero)
- Bits 63:4: TR Dequeue Pointer
Rename 'SCTX_DEQ_MASK' macro to 'TR_DEQ_PTR_MASK' for better clarity.
The acronym "SCTX" stands for Stream Context, but the TR Dequeue Pointer
is not exclusively for Stream Context.
Use GENMASK_ULL() to get mask for bits 63:4 instead of inverted 3:0 mask.
Signed-off-by: Niklas Neronin <niklas.neronin@xxxxxxxxxxxxxxx>
---
drivers/usb/host/xhci-ring.c | 4 ++--
drivers/usb/host/xhci.h | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index d4ec1e707107..9ff5ca4d5c1c 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -1448,7 +1448,7 @@ static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
u64 deq;
/* 4.6.10 deq ptr is written to the stream ctx for streams */
if (ep->ep_state & EP_HAS_STREAMS) {
- deq = le64_to_cpu(stream_ctx->stream_ring) & SCTX_DEQ_MASK;
+ deq = le64_to_cpu(stream_ctx->stream_ring) & TR_DEQ_PTR_MASK;
/*
* Cadence xHCI controllers store some endpoint state
@@ -1464,7 +1464,7 @@ static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
stream_ctx->reserved[1] = 0;
}
} else {
- deq = le64_to_cpu(ep_ctx->deq) & SCTX_DEQ_MASK;
+ deq = le64_to_cpu(ep_ctx->deq) & TR_DEQ_PTR_MASK;
}
xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
"Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 8c164340a2c3..621ffe9df283 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -500,7 +500,8 @@ struct xhci_ep_ctx {
/* deq bitmasks */
#define EP_CTX_CYCLE_MASK (1 << 0)
-#define SCTX_DEQ_MASK (~0xfL)
+/* bits 63:4 - TR Dequeue Pointer */
+#define TR_DEQ_PTR_MASK GENMASK_ULL(63, 4)
/**
--
2.47.2
