From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
On the Renesas RZ/G3S SoC, the USB PHY receives a signal from the system
controller that need to be de-asserted/asserted when power is turned
on/off. This signal, called PWRRDY, is controlled through a specific
register in the system controller memory space.
Add the renesas,sysc-signal DT property to describe the relation b/w the
system controller and the USB PHY on the Renesas RZ/G3S. This property
provides a phandle to the system controller, along with the offset within
the system controller memory space that manages the signal and a bitmask
that indicates the specific bits required to control the signal.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
Changes in v2:
- none; this patch is new
.../bindings/phy/renesas,usb2-phy.yaml | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 2babd200bd98..3b8dcacc3740 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -85,6 +85,16 @@ properties:
dr_mode: true
+ renesas,sysc-signal:
+ description: System controller phandle, specifying the register
+ offset and bitmask associated with a specific system controller signal
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: system controller phandle
+ - description: register offset associated with a signal
+ - description: register bitmask associated with a signal
+
if:
properties:
compatible:
@@ -112,6 +122,18 @@ allOf:
required:
- resets
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,usb2-phy-r9a08g045
+ then:
+ required:
+ - renesas,sysc-signal
+ else:
+ properties:
+ renesas,sysc-signal: false
+
additionalProperties: false
examples:
--
2.39.2
