Currently if the maximum-speed is set to Super Speed for a 3.1 Gen2 capable controller, the FORCE_GEN1 bit of LLUCTL register is set only for one SuperSpeed port (or the first port) present. Modify the logic to set the FORCE_GEN1 bit for all ports if speed is being limited to Gen-1. Suggested-by: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx> --- Suggestion provided for the same at: https://lore.kernel.org/all/20230517003037.i7hsg6k5fn4eyvgf@xxxxxxxxxxxx/ This patch has only been compile tested due to unavailability of hardware at the moment. drivers/usb/dwc3/core.c | 10 +++++++--- drivers/usb/dwc3/core.h | 2 +- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9b888d33e64d..67aefdbe1d5f 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1470,9 +1470,13 @@ static int dwc3_core_init(struct dwc3 *dwc) if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && (DWC3_IP_IS(DWC31)) && dwc->maximum_speed == USB_SPEED_SUPER) { - reg = dwc3_readl(dwc->regs, DWC3_LLUCTL); - reg |= DWC3_LLUCTL_FORCE_GEN1; - dwc3_writel(dwc->regs, DWC3_LLUCTL, reg); + int i; + + for (i = 0; i < dwc->num_usb3_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i)); + reg |= DWC3_LLUCTL_FORCE_GEN1; + dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg); + } } return 0; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index eaa55c0cf62f..296cbe85a494 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -179,7 +179,7 @@ #define DWC3_OEVTEN 0xcc0C #define DWC3_OSTS 0xcc10 -#define DWC3_LLUCTL 0xd024 +#define DWC3_LLUCTL(n) (0xd024 + ((n) * 0x80)) /* Bit fields */ -- 2.34.1
