On 8/27/24 1:31 PM, Mathias Nyman wrote:
Should be harmless, the cycle bit and capital 'C' changes each time the ringbuffer wraps around. This is how TRB consumers/producers keep track of where we are in the ring. segs 1 vs 2 just tells that we have allocated 2 segments for *Intel host event ringbuffer while only one for Renesas.
OK, thanks for that explanation. I uploaded the full Intel controller trace here (curl'able link): https://uni-bielefeld.sciebo.de/s/0O4XIzW529sKYQM/download And here is the Renesas trace: https://uni-bielefeld.sciebo.de/s/jB4qqFL0okPlYwN/download Another difference which I find maybe more interesting then. If you scroll down to where the steady state has been reached, e.g. timestamp 119173.008004 for the Intel trace and timestamp 564371.959089 for the Renesas trace, then there are always 8 xhci_handle_transfer calls for TDs of size 48 and 8 queue_trb calls between doorbell rings for the Renesas controller, but for the Intel controller it looks different: There are also always 8 xhci_queue_trb calls, but either 7 or 9 xhci_handle_transfer calls. This is quite odd, no? Kind
