On 8/25/24 5:15 PM, Michał Pecio wrote:
What is the last digit of your HCSPARAMS2 register? Here's my three hosts, guess which is the one with problems. grep HCSPARAMS2 /sys/kernel/debug/usb/xhci/*/reg-cap /sys/kernel/debug/usb/xhci/0000:02:00.0/reg-cap:HCSPARAMS2 = 0xfc0000fa /sys/kernel/debug/usb/xhci/0000:03:00.0/reg-cap:HCSPARAMS2 = 0xfc000031 /sys/kernel/debug/usb/xhci/0000:04:00.0/reg-cap:HCSPARAMS2 = 0x00000011
Well, the only one with IST[3] set is 0000:02:00.0 and not only that, but 0x0A & 0x07 == 2 so it wants the TRBs at least 2 _frames_ == 2 ms ahead of time. Or did I completely miss something here? :)
See xHCI section 5.3.4. If IST is high, you are probably out of luck.
In my case (on the N97 system) it's a little different though: # grep HCSPARAMS2 /sys/kernel/debug/usb/xhci/0000\:00\:14.0/reg-cap HCSPARAMS2 = 0x14200054 == b00010 1 00001 0000000000000 0101 0100 IST[3] is low, and IST[2:0] == 4, so I would expect that (taking paragraph 2 of xHCI section 4.14.2.1.4 into account) 1 ms would be enough: 4 + 1 microframes == 675 us. On my N100 system, the working Renesas controller has: /sys/kernel/debug/usb/xhci/0000:01:00.0/reg-cap:HCSPARAMS2 = 0x24000011 1 (+1) microframes - not too shabby. And the Intel one: /sys/kernel/debug/usb/xhci/0000:00:14.0/reg-cap:HCSPARAMS2 = 0x14200054 again the same as on my N97 system. BTW: Should I still try your 2 patches from the earlier email? Kind regards, FPS
