From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> The RZ/G3S SYS Controller has 2 registers (one for PCIE one for USB) that need to be configured before/after powering off/on the PCI or USB ares. The bits in these registers control signals to PCIE and USB that need to be de-asserted/asserted after/before power on/off event. For this add SYSC controller driver that registers a reset controller driver on auxiliary bus which allows USB, PCIE drivers to control these signals. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> --- Hi, Philipp, Ulf, Geert, all, In this series the control of USB and PCIE signals was implemented though a reset control driver. This approach was chosen as a result of looking though the HW manual and trying to understand how these signals behave. HW manual can be downloaded from [1] (download manual hardware button -> confirm -> extract archive -> Deliverables -> r01uh1014ej0110-rzg3s.pdf). The description of the USB and PCIE control registers is as follows: SYS_USB_PWRRDY Register (Signal is called PWRRDY), Chapter 6.3.83: Controls PWRRDY terminal of USB: 0: PWRRDY 1: PWRRDY down When turning off the USB region power, set this bit to 1. When turning on the USB region power, set this bit to 0. SYS_PCIE_RST_RSM_B (Signal is called RST_RSM_B), Chapter 6.3.84: Controls RST_RSM_B terminal of PCIe 0: RST_RSM_B=0 1: RST_RSM_B=1 Set RST_RSM_B=1 after PCIe power is applied. When the power in the PCIe region is turned off, set RST_RSM_B=0 before turning off the power supply.
