We can imagine that logically the EC is a device that has some number of
DisplayPort (DP) connector inputs, some number of USB3 connector inputs,
and some number of USB type-c connector outputs. If you squint enough it
looks like a USB type-c dock. Logically there's a crossbar pin
assignment capability within the EC that can assign USB and DP lanes to
USB type-c lanes in the connector (i.e. USB type-c pin configurations).
In reality, the EC is a microcontroller that has some TCPCs and
redrivers connected to it over something like i2c and DP/USB from the AP
is wired directly to those ICs, not the EC.
This design allows the EC to abstract many possible USB and DP hardware
configurations away from the AP (kernel) so that the AP can largely deal
with USB and DP without thinking about USB Type-C much at all. The DP
and USB data originate in the AP, not the EC, so it helps to think that
the EC takes the DP and USB data as input to mux onto USB type-c ports
even if it really doesn't do that. With this split design, the EC
forwards the DP HPD state to the DP hardware via a GPIO that's connected
to the DP phy.
Having that HPD state signaled directly to the DP phy uses precious
hardware resources, a pin or two and a wire, and it also forces the TCPM
to live on the EC. If we want to save costs and move more control of USB
type-c to the kernel it's in our interest to get rid of the HPD pin
entirely and signal HPD to the DP phy some other way. Luckily, the EC
already exposes information about the USB Type-C stack to the kernel via
the host command interface in the "google,cros-ec-typec" compatible
driver, which parses EC messages related to USB type-c and effectively
"replays" those messages to the kernel's USB typec subsystem. This
includes the state of HPD, which can be interrogated and acted upon by
registering a 'struct typec_mux_dev' with the typec subsystem or by
hooking directly into this cros_ec_typec driver.
On DT based systems, the DP display pipeline is abstracted via a 'struct
drm_bridge'. If we want to signal HPD state from within the kernel we
need to hook into the drm_bridge framework somehow to call
drm_bridge_hpd_notify() when HPD state changes in the typec framework.
Use the newly added drm_dp_typec_bridge code to do this. When the EC
notifies AP of a type-c event, look at the port state and set the
connector state to connected or disconnected based on the HPD level when
the port is in DP mode.
Luckily all this logic is already handled by the drm_dp_typec bridge.
Register a bridge when this DT node has the 'mode-switch' property. When
cros_typec_configure_mux() puts a port into DP mode, the mode switch
registered in the drm_dp_typec bridge driver will signal HPD state to
the drm_bridge chain because the typec subsystem will configure the usbc
switches connected to the port with the data this driver provides.
Cc: Prashant Malani <pmalani@xxxxxxxxxxxx>
Cc: Benson Leung <bleung@xxxxxxxxxxxx>
Cc: Tzung-Bi Shih <tzungbi@xxxxxxxxxx>
Cc: <chrome-platform@xxxxxxxxxxxxxxx>
Cc: Pin-yen Lin <treapking@xxxxxxxxxxxx>
Signed-off-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
---
drivers/platform/chrome/Kconfig | 1 +
drivers/platform/chrome/cros_ec_typec.c | 43 +++++++++++++++++++++++++
drivers/platform/chrome/cros_ec_typec.h | 3 ++
3 files changed, 47 insertions(+)
diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
index 7dbeb786352a..0aee8a77f1d6 100644
--- a/drivers/platform/chrome/Kconfig
+++ b/drivers/platform/chrome/Kconfig
@@ -231,6 +231,7 @@ config CROS_EC_TYPEC
depends on MFD_CROS_EC_DEV && TYPEC
depends on CROS_USBPD_NOTIFY
depends on USB_ROLE_SWITCH
+ select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
default MFD_CROS_EC_DEV
help
If you say Y here, you get support for accessing Type C connector
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index 4d305876ec08..f7e184fa90c5 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -9,6 +9,7 @@
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_graph.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_usbpd_notify.h>
#include <linux/platform_device.h>
@@ -16,11 +17,18 @@
#include <linux/usb/typec_dp.h>
#include <linux/usb/typec_tbt.h>
+#include <drm/bridge/aux-bridge.h>
+
#include "cros_ec_typec.h"
#include "cros_typec_vdm.h"
#define DRV_NAME "cros-ec-typec"
+struct cros_typec_dp_bridge {
+ struct cros_typec_data *typec_data;
+ struct drm_dp_typec_bridge_dev *dev;
+};
+
#define DP_PORT_VDO (DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_C) | BIT(DP_PIN_ASSIGN_D)) | \
DP_CAP_DFP_D | DP_CAP_RECEPTACLE)
@@ -334,6 +342,9 @@ static int cros_typec_init_ports(struct cros_typec_data *typec)
u32 port_num = 0;
nports = device_get_child_node_count(dev);
+ /* Don't count any 'ports' child node */
+ if (of_graph_is_present(dev->of_node))
+ nports--;
if (nports == 0) {
dev_err(dev, "No port entries found.\n");
return -ENODEV;
@@ -347,6 +358,10 @@ static int cros_typec_init_ports(struct cros_typec_data *typec)
/* DT uses "reg" to specify port number. */
port_prop = dev->of_node ? "reg" : "port-number";
device_for_each_child_node(dev, fwnode) {
+ /* An OF graph isn't a connector */
+ if (fwnode_name_eq(fwnode, "ports"))
+ continue;
+
if (fwnode_property_read_u32(fwnode, port_prop, &port_num)) {
ret = -EINVAL;
dev_err(dev, "No port-number for port, aborting.\n");
@@ -413,6 +428,30 @@ static int cros_typec_init_ports(struct cros_typec_data *typec)
return ret;
}
+static int cros_typec_init_dp_bridge(struct cros_typec_data *typec)
+{
+ struct device *dev = typec->dev;
+ struct cros_typec_dp_bridge *dp_bridge;
+ struct drm_dp_typec_bridge_dev *dp_dev;
+
+ /* Not capable of DP altmode switching. Ignore. */
+ if (!fwnode_property_read_bool(dev_fwnode(dev), "mode-switch"))
+ return 0;
+
+ dp_bridge = devm_kzalloc(dev, sizeof(*dp_bridge), GFP_KERNEL);
+ if (!dp_bridge)
+ return -ENOMEM;
+ typec->dp_bridge = dp_bridge;
+ dp_bridge->typec_data = typec;
+
+ dp_dev = devm_drm_dp_typec_bridge_alloc(dev, dev->of_node);
+ if (IS_ERR(dp_dev))
+ return PTR_ERR(dp_dev);
+ dp_bridge->dev = dp_dev;
+
+ return devm_drm_dp_typec_bridge_add(dev, dp_dev);
+}
+
static int cros_typec_usb_safe_state(struct cros_typec_port *port)
{
int ret;
@@ -1257,6 +1296,10 @@ static int cros_typec_probe(struct platform_device *pdev)
typec->num_ports = EC_USB_PD_MAX_PORTS;
}
+ ret = cros_typec_init_dp_bridge(typec);
+ if (ret < 0)
+ return ret;
+
ret = cros_typec_init_ports(typec);
if (ret < 0)
return ret;
diff --git a/drivers/platform/chrome/cros_ec_typec.h b/drivers/platform/chrome/cros_ec_typec.h
index deda180a646f..73d300427140 100644
--- a/drivers/platform/chrome/cros_ec_typec.h
+++ b/drivers/platform/chrome/cros_ec_typec.h
@@ -27,6 +27,8 @@ struct cros_typec_altmode_node {
struct list_head list;
};
+struct cros_typec_dp_bridge;
+
/* Platform-specific data for the Chrome OS EC Type C controller. */
struct cros_typec_data {
struct device *dev;
@@ -35,6 +37,7 @@ struct cros_typec_data {
unsigned int pd_ctrl_ver;
/* Array of ports, indexed by port number. */
struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS];
+ struct cros_typec_dp_bridge *dp_bridge;
struct notifier_block nb;
struct work_struct port_work;
bool typec_cmd_supported;
--
https://chromeos.dev
