On Fri, Jun 07, 2024, joswang wrote:
> My initial idea was similar to yours,Please help review the following changes.
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 3a8fbc2d6b99..8c6a09718737 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -961,11 +961,15 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc)
> static void dwc3_core_setup_global_control(struct dwc3 *dwc)
> {
> u32 reg;
> + unsigned int power_opt;
> + unsigned int hw_mode;
Use reverse christmas tree declaration style:
type1 abcdefg
type2 abcde
type3 abc
>
> reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> + power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
>
> - switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
> + switch (power_opt) {
> case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> /**
> * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
> @@ -998,6 +1002,18 @@ static void dwc3_core_setup_global_control(struct dwc3
> *dwc)
> break;
> }
>
> + /*
> + * WORKAROUND: DWC_usb31 version 2.00a have an issue that would
> + * cause a CSR read timeout When CSR read coincides with RAM
> + * Clock Gating Entry.
Note in the comment and commit message that this applies while operating
as host mode. Add the STAR number reference in the commit message.
> + *
> + * This workaround solution disable Clock Gating, sacrificing
> + * power consumption for normal operation.
> + */
> + if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
> + hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
> + reg |= DWC3_GCTL_DSBLCLKGTNG;
> +
Thanks,
Thinh
