On 03/06/2024 10:36, Jung Daehwan wrote: > On Mon, Jun 03, 2024 at 08:57:16AM +0200, Krzysztof Kozlowski wrote: >> On 03/06/2024 05:03, Jung Daehwan wrote: >>> On Fri, May 31, 2024 at 10:10:30AM +0200, Krzysztof Kozlowski wrote: >>>> On 31/05/2024 08:07, Daehwan Jung wrote: >>>>> Add a new quirk for dwc3 core to support writing high-low order. >>>> >>>> This does not tell me more. Could be OS property as well... please >>>> describe hardware and provide rationale why this is suitable for >>>> bindings (also cannot be deduced from compatible). >>>> >>>> >>> >>> Hi, >>> >>> I'm sorry I didn't describe it in dt-bindings patches. >>> It's described in cover-letter and other patches except in dt-bindings. >>> I will add it in next submission. >>> >>> I've found out the limitation of Synopsys dwc3 controller. This can work >>> on Host mode using xHCI. A Register related to ERST should be written >>> high-low order not low-high order. Registers are always written low-high order >>> following xHCI spec.(64-bit written is done in each 2 of 32-bit) >>> That's why new quirk is needed for workaround. This quirk is used not in >>> dwc3 controller itself, but passed to xhci quirk eventually. That's because >>> this issue occurs in Host mode using xHCI. >>> >> >> If there is only one register then you should just program it >> differently and it does not warrant quirk property. >> > > Could you tell me why you think it does not warrant? I think this is > good to use quirk. Because it is a fixed case, deduced from compatible. No need for a property for this. Best regards, Krzysztof
