On 22.5.2024 4.03, Daehwan Jung wrote:
ERSTBA_HI should be written first on secondary interrupter.
That's why secondary interrupter could be set while Host Controller
is already running.
[Synopsys]- The host controller was design to support ERST setting
during the RUN state. But since there is a limitation in controller
in supporting separate ERSTBA_HI and ERSTBA_LO programming,
It is supported when the ERSTBA is programmed in 64bit,
or in 32 bit mode ERSTBA_HI before ERSTBA_LO
xHCI specification 5.1 "Register Conventions "states that 64 bit
registers should be written in low-high order
[Synopsys]- The internal initialization of event ring fetches
the "Event Ring Segment Table Entry" based on the indication of
ERSTBA_LO written.
Any idea if this is a common issue with this host?
Should other 64 bit registers also be written in reverse order.
Signed-off-by: Daehwan Jung <dh10.jung@xxxxxxxxxxx>
---
drivers/usb/host/xhci-mem.c | 5 ++++-
drivers/usb/host/xhci.h | 6 ++++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 3100219..36ee704 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -2325,7 +2325,10 @@ xhci_add_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
erst_base &= ERST_BASE_RSVDP;
erst_base |= ir->erst.erst_dma_addr & ~ERST_BASE_RSVDP;
- xhci_write_64(xhci, erst_base, &ir->ir_set->erst_base);
+ if (intr_num == 0)
+ xhci_write_64(xhci, erst_base, &ir->ir_set->erst_base);
+ else
+ xhci_write_64_r(xhci, erst_base, &ir->ir_set->erst_base);
This may cause issues with other hosts expecting low-high order as stated
in the specification.
If all 64 bit registers should be written in high-low order for this host then
maybe set a quirk flag and change xhci_write_64()instead.
xhci_write_64(...)
{
if (xhci->quirks & XHCI_WRITE_64_HI_LO)
hi_lo_writeq(val, regs);
else
lo_hi_writeq(val, regs);
}
Thanks
Mathias
