On Fri, Feb 23, 2024, Thinh Nguyen wrote:
> On Sat, Feb 24, 2024, Radhey Shyam Pandey wrote:
> > From: Piyush Mehta <piyush.mehta@xxxxxxx>
> >
> > The GSBUSCFG0 register bits [31:16] are used to configure the cache type
> > settings of the descriptor and data write/read transfers (Cacheable,
> > Bufferable/ Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0
> > cache bits must be updated to support CCI enabled transfers in USB.
> >
> > Signed-off-by: Piyush Mehta <piyush.mehta@xxxxxxx>
> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx>
> > ----
> > changes for v2:
> > Make GSBUSCFG0 configuration specific to AMD-xilinx platform.
> > Taken reference from existing commit ec5eb43813a4 ("usb: dwc3: core:
> > add support for realtek SoCs custom's global register start address")
Regarding that change from Realtek, it's a special case. I want to avoid
doing platform specific checks in the core.c if possible. Eventually, I
want to move that logic from Realtek to its glue driver.
BR,
Thinh
> >
> > v1 link:
> > https://urldefense.com/v3/__https://lore.kernel.org/all/20231013053448.11056-1-piyush.mehta@amd.com__;!!A4F2R9G_pg!ffADlNJmRyCb1C2B0z21-8AbJE4YDyiXNxKBKBqmhmBOSSZBokHS_qyetGEqb7Cwawe0Wvbz2aqSZz_bTfvS0cXdwXLVWw$
>
> Please check the comment from the previous thread:
> https://lore.kernel.org/linux-usb/20240223224744.vptvfkqzgqv24ptz@xxxxxxxxxxxx/T/#t
>
