On Wed, Feb 14, 2024, Roger Quadros wrote: > TRM information is outdated and design team has confirmed > that PHY_CORE_VOLTAGE should be 0 irrespective of > VDD_CORE voltage. > > Signed-off-by: Roger Quadros <rogerq@xxxxxxxxxx> > --- > Changelog: > > v3: no change > > v2: no change > https://urldefense.com/v3/__https://lore.kernel.org/all/20240205141221.56076-4-rogerq@xxxxxxxxxx/__;!!A4F2R9G_pg!YRbEcs6kcWbVmZ0bBu9SvOEAnSFUPv-Zzpt-zLtFZFLdhquAp5tppvikEqMuGTcFuQAXksPiBmc-zuZqrvmN$ > > v1: https://urldefense.com/v3/__https://lore.kernel.org/all/20240201121220.5523-4-rogerq@xxxxxxxxxx/__;!!A4F2R9G_pg!YRbEcs6kcWbVmZ0bBu9SvOEAnSFUPv-Zzpt-zLtFZFLdhquAp5tppvikEqMuGTcFuQAXksPiBmc-zlgvqaS8$ > --- > drivers/usb/dwc3/dwc3-am62.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c > index 600ba9cfefea..af1ce934e7fb 100644 > --- a/drivers/usb/dwc3/dwc3-am62.c > +++ b/drivers/usb/dwc3/dwc3-am62.c > @@ -97,7 +97,8 @@ > #define USBSS_VBUS_STAT_SESSVALID BIT(2) > #define USBSS_VBUS_STAT_VBUSVALID BIT(0) > > -/* Mask for PHY PLL REFCLK */ > +/* USB_PHY_CTRL register bits in CTRL_MMR */ > +#define PHY_CORE_VOLTAGE_MASK BIT(31) > #define PHY_PLL_REFCLK_MASK GENMASK(3, 0) > > #define DWC3_AM62_AUTOSUSPEND_DELAY 100 > @@ -162,6 +163,13 @@ static int phy_syscon_pll_refclk(struct dwc3_am62 *am62) > > am62->offset = args.args[0]; > > + /* Core voltage. PHY_CORE_VOLTAGE bit Recommended to be 0 always */ > + ret = regmap_update_bits(am62->syscon, am62->offset, PHY_CORE_VOLTAGE_MASK, 0); > + if (ret) { > + dev_err(dev, "failed to set phy core voltage\n"); > + return ret; > + } > + > ret = regmap_update_bits(am62->syscon, am62->offset, PHY_PLL_REFCLK_MASK, am62->rate_code); > if (ret) { > dev_err(dev, "failed to set phy pll reference clock rate\n"); > > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> Thinh
