XHCI_SG_TRB_CACHE_SIZE_QUIRK was introduced in XHCI to resolve XHC timeout while using SG buffers, which was seen Synopsys XHCs. The support for this isn't present in DWC3 layer, this series enables XHCI_SG_TRB_CACHE_SIZE_QUIRK since this is needed for DWC3 controller. In Synopsys DWC3 databook, Table 9-3: xHCI Debug Capability Limitations Chained TRBs greater than TRB cache size: The debug capability driver must not create a multi-TRB TD that describes smaller than a 1K packet that spreads across 8 or more TRBs on either the IN TR or the OUT TR. More information about this XHCI quirk is mentioned on the following thread. https://lore.kernel.org/all/20201208092912.1773650-3-mathias.nyman@xxxxxxxxxxxxxxx/ Changes in v3: Updated the props[] array size from 4 to 5 in dwc3/host.c Changes in v2: Changed implementation using device property instead of priv_data Split the single patch into 2 patch series, v1 is mentioned below https://lore.kernel.org/all/20231121135936.1669167-1-quic_prashk@xxxxxxxxxxx/ Prashanth K (2): usb: host: xhci-plat: Add support for XHCI_SG_TRB_CACHE_SIZE_QUIRK usb: dwc3: host: Set XHCI_SG_TRB_CACHE_SIZE_QUIRK drivers/usb/dwc3/host.c | 4 +++- drivers/usb/host/xhci-plat.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) -- 2.25.1
