On 8.12.2023 23.04, Sam Edwards wrote:
Hi USB devs, This patchset is a semi-RFC: I haven't discussed this change yet, and it may turn out to be a bad idea. But if there is a consensus that this change is appropriate, these patches are the ones I'd submit for inclusion. These patches were developed while working with a SoC (Rockchip RK3588) that contains DWC3-OTG controllers and accompanying USB2 + USB3/DP PHYs. My target (Turing RK1) uses its first bus in USB2.0-OTG mode only: the associated USB3 PHY is reserved for DP. Worse, a driver for the USBDP block (though it exists) has not been merged to mainline. Without lighting up the PHY side of the PIPE, the DWC3 behaves erratically, even for USB2 operation. This could be addressed by patching in the (out-of-tree) USBDP driver and enabling only its USB backend. However, I found it cleaner (also from a user-friendliness standpoint) just to disable the unusable USB3 port. These patches achieve that by (1) making it possible to tell the xHCI driver to ignore any USB3 port(s), and (2) (perhaps more controversially) making the DWC3 driver disable USB3 host ports when `maximum-speed` isn't set high enough.
I don't think this will work as a generic xhci driver feature. Even if we ignore all USB3 ports in software they will for most xHC hosts be powered and enabled in hardware by default after controller reset. This means they perform link training, generate all kinds of events with interrupts (connect, over-current etc) that driver now can't handle. Sound like the setup you are using has a very specific issue, and it would need a narrow targeted quirk to solve it.
There are other ways to disable the USB3 ports on RK3588, such as via some syscon registers. I figured I would start with the most general solution (benefitting other SoCs) first, getting more specific only if necessary. :)
To me a specific solution to a specific problem like this sounds better. Thanks Mathias
