On Mon, Dec 04, 2023 at 12:25:38PM +0200, Mika Westerberg wrote:
> From: Gil Fine <gil.fine@xxxxxxxxxxxxxxx>
>
> With the current bandwidth allocation we end up reserving too much for the USB
> 3.x and PCIe tunnels that leads to reduced capabilities for the second
> DisplayPort tunnel.
>
> Fix this by decreasing the USB 3.x allocation to 900 Mb/s which then allows
> both tunnels to get the maximum HBR2 bandwidth. This way, the reserved
> bandwidth for USB 3.x and PCIe, would be 1350 Mb/s (taking weights of USB 3.x
> and PCIe into account). So bandwidth allocations on a link are:
> USB 3.x + PCIe tunnels => 1350 Mb/s
> DisplayPort tunnel #1 => 17280 Mb/s
> DisplayPort tunnel #2 => 17280 Mb/s
>
> Total consumed bandwidth is 35910 Mb/s. So that all the above can be tunneled
> on a Gen 3 link (which allows maximum of 36000 Mb/s).
>
> Fixes: 582e70b0d3a4 ("thunderbolt: Change bandwidth reservations to comply USB4 v2")
> Signed-off-by: Gil Fine <gil.fine@xxxxxxxxxxxxxxx>
> Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
Applied to thunderbolt.git/fixes.
