The GSBUSCFG0 register bits [31:16] are used to configure the cache type settings of the descriptor and data write/read transfers (Cacheable, Bufferable/ Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0 cache bits must be updated to support CCI enabled transfers in USB. Signed-off-by: Piyush Mehta <piyush.mehta@xxxxxxx> --- DWC3 Register Map Link: https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/GSBUSCFG0-USB3_XHCI-Register Register Name GSBUSCFG0 Description Global SoC Bus Configuration Register 0 GSBUSCFG0 (USB3_XHCI) Register Bit-Field: DATRDREQINFO 31:28 DESRDREQINFO 27:24 DATWRREQINFO 23:20 DESWRREQINFO 19:16 --- drivers/usb/dwc3/core.c | 17 +++++++++++++++++ drivers/usb/dwc3/core.h | 5 +++++ 2 files changed, 22 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9c6bf054f15d..fc6892c63abf 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -23,6 +23,7 @@ #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/of_graph.h> #include <linux/acpi.h> #include <linux/pinctrl/consumer.h> @@ -559,6 +560,20 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); } +static void dwc3_config_soc_bus(struct dwc3 *dwc) +{ + if (of_dma_is_coherent(dwc->dev->of_node)) { + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + reg |= DWC3_GSBUSCFG0_DATRDREQINFO_MASK | + DWC3_GSBUSCFG0_DESRDREQINFO_MASK | + DWC3_GSBUSCFG0_DATWRREQINFO_MASK | + DWC3_GSBUSCFG0_DESWRREQINFO_MASK; + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg); + } +} + static int dwc3_core_ulpi_init(struct dwc3 *dwc) { int intf; @@ -1137,6 +1152,8 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_set_incr_burst_type(dwc); + dwc3_config_soc_bus(dwc); + ret = dwc3_phy_power_on(dwc); if (ret) goto err_exit_phy; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index a69ac67d89fe..bd937025ce05 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -173,6 +173,11 @@ #define DWC3_OSTS 0xcc10 /* Bit fields */ +/* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */ +#define DWC3_GSBUSCFG0_DATRDREQINFO_MASK GENMASK(31, 28) +#define DWC3_GSBUSCFG0_DESRDREQINFO_MASK GENMASK(27, 24) +#define DWC3_GSBUSCFG0_DATWRREQINFO_MASK GENMASK(23, 20) +#define DWC3_GSBUSCFG0_DESWRREQINFO_MASK GENMASK(19, 16) /* Global SoC Bus Configuration INCRx Register 0 */ #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ -- 2.17.1
