On Thu, Oct 12, 2023, Ladislav Michl wrote:
> From: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
>
> Implement workaround for Octeon Known Issue Id 29206:
> | The USB high speed logic contains a PLL that must lock during
> | initialization for correct operation. In very rare circumstances,
> | it is possible for the PLL to fail to start correctly.
> | Workaround
> | After initialization, check the USB PLL lock register via the
> | UPHY CR interface. If the PLL is not running, power it down and
> | back up and restart the initialization.
Minor nit: Can we replace "|" with tabs. I think it's easier to read.
>
> PLL initialization code taken from Cavium's vendor bootloader:
> u-boot/drivers/usb/host/xhci-octeon.c:octeon3_usb_clocks_start
>
> Signed-off-by: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
> ---
> NOTE:
> This patch fixes initialization issue found on some CN7020 based boards.
> Without this patch, controller sometimes fails to detect devices connected.
> Original code comes from Cavium released u-boot monster patch, which seems
> to suffer from mistakes made while resolving merge conflicts when upgrading
> to newer u-boot.
> Testing revealed that only single reinit is needed to properly lock PLL,
> this agrees with comment in Cavium's u-boot code, which is claiming the
> same. However, same as in u-boot code, reinit is attempted three times.
> (in could be done using while loop instead of goto, just let me know
> which way do you prefer)
> SoCs suffering from this problem would fail to initialize PHY about
> several tens times of thousand boots. This patch always restored
> functional state.
What kernel version did you use? Perhaps it has the same issue due to
the commit e835c0a4e23c ("usb: dwc3: don't reset device side if dwc3 was
configured as host-only")
Did you test this against Greg's usb-linus branch with the fix for the
above?
Thanks,
Thinh
