Add a reset-controller for supporting Xilinx versal platforms. To reset
the USB controller, get the reset ID from device-tree and using ID trigger
the reset, with the assert and deassert reset controller APIs for USB
controller initialization. Delay of microseconds is added in between assert
and deassert to meet the setup and hold the time requirement of the reset.
Signed-off-by: Piyush Mehta <piyush.mehta@xxxxxxx>
---
drivers/usb/dwc3/dwc3-xilinx.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index 19307d24f3a0..d0780bf231fb 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -32,9 +32,6 @@
#define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
#define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
-/* Versal USB Reset ID */
-#define VERSAL_USB_RESET_ID 0xC104036
-
#define XLNX_USB_FPD_PIPE_CLK 0x7c
#define PIPE_CLK_DESELECT 1
#define PIPE_CLK_SELECT 0
@@ -72,20 +69,26 @@ static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
{
struct device *dev = priv_data->dev;
+ struct reset_control *crst;
int ret;
+ crst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(crst))
+ return dev_err_probe(dev, PTR_ERR(crst), "failed to get reset signal\n");
+
dwc3_xlnx_mask_phy_rst(priv_data, false);
/* Assert and De-assert reset */
- ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
- PM_RESET_ACTION_ASSERT);
+ ret = reset_control_assert(crst);
if (ret < 0) {
dev_err_probe(dev, ret, "failed to assert Reset\n");
return ret;
}
- ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
- PM_RESET_ACTION_RELEASE);
+ /* reset hold time */
+ usleep_range(5, 10);
+
+ ret = reset_control_deassert(crst);
if (ret < 0) {
dev_err_probe(dev, ret, "failed to De-assert Reset\n");
return ret;
--
2.17.1
