On Wed, 30 Aug 2023 at 21:30, Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx> wrote: > > Add USB phy and controller nodes. > > Co-developed-by: Amandeep Singh <quic_amansing@xxxxxxxxxxx> > Signed-off-by: Amandeep Singh <quic_amansing@xxxxxxxxxxx> > Signed-off-by: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx> > --- > V2: > Fix ordering of the USB related nodes and use > generic node names. > --- > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > index 9f13d2dcdfd5..917e4a2d8e64 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > @@ -93,6 +93,19 @@ > #size-cells = <1>; > ranges = <0 0 0 0xffffffff>; > > + usbphy0: phy@5b000 { > + compatible = "qcom,ipq5018-usb-hsphy"; > + reg = <0x0005b000 0x120>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > tlmm: pinctrl@1000000 { > compatible = "qcom,ipq5018-tlmm"; > reg = <0x01000000 0x300000>; > @@ -155,6 +168,47 @@ > status = "disabled"; > }; > > + usb: usb@8af8800 { > + compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; > + reg = <0x08af8800 0x400>; > + > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq"; > + > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "core", > + "iface", > + "sleep", > + "mock_utmi"; > + > + resets = <&gcc GCC_USB0_BCR>; > + > + qcom,select-utmi-as-pipe-clk; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + status = "disabled"; > + > + usb2_0_dwc: usb@8a00000 { As we have seen from the next patchset, this host supports USB 3.0. Can you please drop the 2_0 part of the label? > + compatible = "snps,dwc3"; > + reg = <0x08a00000 0xe000>; > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "ref"; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + phy-names = "usb2-phy"; > + phys = <&usbphy0>; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + }; > + }; > + > intc: interrupt-controller@b000000 { > compatible = "qcom,msm-qgic2"; > reg = <0x0b000000 0x1000>, /* GICD */ > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > -- With best wishes Dmitry